MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 375

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

D.7.1 BIU Module Configuration Register
BIUMCR — BIU Module Configuration Register
STOP — Low-Power Stop Mode Enable
FRZ — FREEZE Assertion Response
VECT[7:6] — Interrupt Vector Base Number
MC68336/376
USER’S MANUAL
STOP
15
0
RESET:
When the STOP bit is set, the clock to the CTM4 is shutdown, placing the module into
low-power stop mode. The BIUSM still operates in low-power stop mode, allowing the
submodule control and data registers to be accessed.
The FRZ bit controls CTM4 response to assertion of the IMB FREEZE signal. Since
the BIUSM propagates FREEZE to the CTM4 submodules via the submodule bus, the
setting of FRZ affects all CTM4 submodules.
This bit field selects the base interrupt vector number for the CTM4. Of the eight bits
necessary for a vector number, the six low-order bits are hardware defined on a sub-
module basis, while the two remaining bits are provided by VECT[7:6]. This places the
CTM4 vectors in one of four possible positions in the interrupt vector table. Refer to
Table D-36.
0 = Enable CTM4 clocks.
1 = Disable CTM4 clocks.
0 = CTM4 ignores the IMB FREEZE signal.
1 = CTM4 submodules freeze when the IMB FREEZE signal is asserted.
$YFF464 – $YFF4FE
FRZ
14
NOTES:
0
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
Address
$YFF45C
$YFF45A
$YFF45E
$YFF460
$YFF462
USED
NOT
13
Table D-36 Interrupt Vector Base Number Bit Field
1
12
1
VECT[7:6]
Table D-35 CTM4 Address Map (Continued)
VECT7
0
0
1
1
11
15
1
10
0
FCSM12 Status/Interrupt/Control Register (FCSM12SIC)
IARB[2:0]
VECT6
REGISTER SUMMARY
9
0
0
1
0
1
MCSM11 Modulus Latch (MCSM11ML)
MCSM11 Counter (MCSM11CNT)
FCSM12 Counter (FCSM12CNT)
8
0
Resulting Base Vector Number
NOT USED
7
Reserved
Reserved
6
$C0
$00
$40
$80
TBRS1
5
0
4
NOT USED
3
2
MOTOROLA
$YFF400
0
1
TBRS0
D-57
0
0