MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 56

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.2.1 Data Registers
4-4
MOTOROLA
The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits and ad-
dresses of 16 or 32 bits. The following data types are supported:
Each of data registers D7–D0 is 32 bits wide. Byte operands occupy the low-order 8
bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits.
When a data register is used as either a source or destination operand, only the ap-
propriate low-order byte or word (in byte or word operations, respectively) is used or
changed; the remaining high-order portion is unaffected. The least significant bit (LSB)
of a long-word integer is addressed as bit zero, and the most significant bit (MSB) is
addressed as bit 31. Figure 4-4 shows the organization of various types of data in the
data registers.
Quad-word data consists of two long words and represents the product of 32-bit mul-
tiply or the dividend of 32-bit divide operations (signed and unsigned). Quad-words
may be organized in any two data registers without restrictions on order or pairing.
There are no explicit instructions for the management of this data type, although the
MOVEM instruction can be used to move a quad-word into or out of the registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form. CPU32
BCD instructions use a format in which a byte contains two digits. The four LSB con-
tain the least significant digit, and the four MSB contain the most significant digit. The
ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single
byte.
• Bits
• Packed Binary-Coded Decimal Digits
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
31
31
Figure 4-3 Supervisor Programming Model Supplement
16
CENTRAL PROCESSOR UNIT
15
15
8 7
2
(CCR)
0
0
0
0
A7’ (SSP)
SR
VBR
SFC
DFC
SUPERVISOR STACK POINTER
VECTOR BASE REGISTER
ALTERNATE FUNCTION
STATUS REGISTER
CODE REGISTERS
USER’S MANUAL
MC68336/376
CPU32 SUPV PROG MODEL