MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 430

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

SIM Reference Manual 5-54
SIMCR 5-2, 9-2, 12-1, D-6
SIMTR D-7
SIMTRE D-9
SIZ 5-22, 5-25, 5-40
Size signals (SIZ) 5-22
Slave select signal (SS) 9-19
SLOCK D-8
SM 11-9
SMB 10-1
SOF 13-9
Soft reset (SOFTRST) D-86
SOFTRST 13-11, D-86
Software
SPACE (address space select) 5-60, D-20
SPBR D-49
SPCR0 D-48
MOTOROLA
I-14
reset 5-40
software watchdog 5-15
spurious interrupt monitor 5-15
system
encoding 5-22
breakpoints 5-31
service register (SWSR) D-14
watchdog 5-15
port F
reset status register (RSR) D-9
software service register (SWSR) D-14
system
test
state of pins 5-46
block diagram (with PIT) 5-15
clock 5-4
configuration 5-2
protection 5-14
block diagram 5-17
clock rate 5-16
enable (SWE) D-12
enable (SWE) bit 5-15
prescale (SWP) D-12
prescale (SWP) bit 5-16
ratio of SWP and SWT bits 5-16
reset (SW) D-9
timeout period calculation 5-16
timing field (SWT) 5-16, D-12
data direction register (DDRF) 5-64, D-11
data register (PORTF) 5-64, D-11
pin assignment register (PFPAR) 5-64,
integration
protection control register (SYPCR) D-12
module
submodule control register (CREG) D-21
block diagram 5-4
synthesizer operation 5-5
test register - ECLK (SIMTRE) D-9
test register (SIMTR) D-7
repetition count (TSTRC) D-21
shift count register (TSTSC) D-21
D-10
D-11
SPCR1 D-50
SPCR2 D-51
SPCR3 D-52
SPE 9-6, D-50
SPI 4-24
SPIF D-53
SPIFIE D-51
SPSR D-52
SPWM 11-7
SR 4-6
SRAM
SRBK D-77
SRR 13-5
SS 9-19, 9-20
SSE1 D-32
SSE2 D-33
SSP 4-10
Stack pointer (SP) 4-1
Standard
Standby RAM module w/ TPU emulation (TPURAM). See
Start
State machine 8-24, 9-28
Stepper motor (SM) 11-9
STEXT 5-12, D-9
STF D-75
STOP 13-17, D-22, D-24, D-28, D-41, D-57, D-73, D-82,
Stop
finished interrupt enable (SPIFIE) D-51
address map D-22
array address mapping 6-1
features 3-1
normal access 6-2
registers
reset 6-3
standby and low-power stop operation 6-2
message format 13-1
nonreturn to zero (NRZ) 9-2
bit (beginning of data frame) 9-25
-of-frame (SOF) symbol 13-9
acknowledge (STOPACK) D-87
clocks to TCRs (CLKS) D-75
enable (STOP) bit
flag (STF) D-75
mode
array base address register
module configuration register (RAMMCR) 6-1,
test register (RAMTST) 6-1, D-23
frames 13-4
TPURAM 12-1
D-85
BIUSM 10-3
QADC 8-6
QSM 9-2
SRAM 6-2
TouCAN 13-17
TPU 11-15
external clock (STEXT) 5-12, D-9
high (RAMBAH) 6-1, D-23
low (RAMBAL) 6-1, D-23
D-22
USER’S MANUAL
MC68336/376