MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 353

MC68376BAMFT20

Manufacturer Part Number
MC68376BAMFT20
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68376BAMFT20

Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Interface Type
QSPI/SCI
Program Memory Type
ROM
Program Memory Size
8KB
Total Internal Ram Size
7.5KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68376BAMFT20
Manufacturer:
FREESCAL
Quantity:
245
QASR — Status Register
BQ2[5:0] — Beginning of Queue 2
D.5.7 QADC Status Register
CF1 — Queue 1 Completion Flag
PF1 — Queue 1 Pause Flag
CF2 — Queue 2 Completion Flag
PF2 — Queue 2 Pause Flag
TOR1 — Queue 1 Trigger Overrun
MC68336/376
USER’S MANUAL
RESET:
CF1
15
0
The BQ2 field indicates the location in the CCW table where queue 2 begins. The BQ2
field also indicates the end of queue 1 and thus creates an end-of-queue condition for
queue 1.
CF1 indicates that a queue 1 scan has been completed. CF1 is set by the QADC when
the conversion is complete for the last CCW in queue 1, and the result is stored in the
result table.
PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the QADC when
the current queue 1 CCW has the pause bit set, the selected input channel has been
converted, and the result has been stored in the result table.
CF2 indicates that a queue 2 scan has been completed. CF2 is set by the QADC when
the conversion is complete for the last CCW in queue 2, and the result is stored in the
result table.
PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the QADC when
the current queue 2 CCW has the pause bit set, the selected input channel has been
converted, and the result has been stored in the result table.
TOR1 indicates that an unexpected queue 1 trigger event has occurred. TOR1 can be
set only while queue 1 is active.
A trigger event generated by a transition on ETRIG1 may be recorded as a trigger
overrun. TOR1 can only be set when using an external trigger mode. TOR1 cannot oc-
cur when the software initiated single-scan mode or the software initiated continuous-
scan mode is selected.
0 = Queue 1 scan is not complete.
1 = Queue 1 scan is complete.
0 = Queue 1 has not reached a pause.
1 = Queue 1 has reached a pause.
0 = Queue 2 scan is not complete.
1 = Queue 2 scan is complete.
0 = Queue 2 has not reached a pause.
1 = Queue 2 has reached a pause.
PF1
14
0
CF2
13
0
PF2
12
0
TOR1
11
0
TOR2
10
0
REGISTER SUMMARY
9
0
8
0
QS[3:0]
7
0
6
0
5
0
4
0
3
0
CWP[5:0]
2
0
$YFFF210
MOTOROLA
1
0
D-35
0
0

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