MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 346

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

QADCMCR — Module Configuration Register
D.5 QADC Module
D.5.1 QADC Module Configuration Register
STOP — Low-Power Stop Mode Enable
D-28
RESET:
MOTOROLA
STOP
15
0
Table D-24 shows the QADC address map. The column labeled “Access” indicates
the privilege level at which the CPU32 must be operating to access the register. A des-
ignation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or
unrestricted access.
When the STOP bit is set, the clock signal to the QADC is disabled, effectively turning
off the analog circuitry.
0 = Enable QADC clock.
1 = Disable QADC clock.
FRZ
14
0
NOTES:
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. Y = M111, where M is the logic state of the module mapping (MM) bit in SIMCR.
—
—
—
—
S
S
S
13
$YFF280 – $YFF2AE
$YFF2B0 – $YFF2FE
$YFF380 – $YFF3AE
$YFF3B0 – $YFF3FE
$YFF212 – $YFF22E
$YFF230 – $YFF27E
$YFF300 – $YFF32E
$YFF330 – $YFF37E
12
Address
$YFF20A
$YFF20C
$YFF20E
$YFF200
$YFF202
$YFF204
$YFF206
$YFF208
$YFF210
11
NOT USED
1
10
Table D-24 QADC Address Map
REGISTER SUMMARY
15
9
Port A Data (PORTQA)
8
Right Justified, Unsigned Result Register (RJURR)
Left Justified, Unsigned Result Register (LJURR)
Left Justified, Signed Result Register (LJSRR)
Module Configuration Register (QADCMCR)
Conversion Command Word (CCW) Table
SUPV
7
1
Port Data Direction Register (DDRQA)
Interrupt Register (QADCINT)
Control Register 0 (QACR0)
Control Register 1 (QACR1)
Control Register 2 (QACR2)
Test Register (QADCTEST)
6
Status Register (QASR)
Result Word Table
Result Word Table
Result Word Table
NOT USED
Reserved
Reserved
Reserved
Reserved
8
5
7
4
Port B Data (PORTQB)
3
0
USER’S MANUAL
2
0
IARB[3:0]
MC68336/376
$YFF200
1
0
0
0
0