MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 335

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

D.2.18 Chip-Select Base Address Register Boot ROM
CSBARBT — Chip-Select Base Address Register Boot ROM
D.2.19 Chip-Select Base Address Registers
CSBAR[0:10] — Chip-Select Base Address Registers
ADDR[23:11] — Base Address
BLKSZ[2:0] — Block Size Field
MC68336/376
USER’S MANUAL
ADDR
ADDR
15
23
15
23
0
0
RESET:
RESET:
Each chip-select pin has an associated base address register. A base address is the
lowest address in the block of addresses enabled by a chip select. CSBARBT contains
the base address for selection of a bootstrap memory device. Bit and field definitions
for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.
This field sets the starting address of a particular chip-select’s address space. The
address compare logic uses only the most significant bits to match an address within
a block. The value of the base address must be an integer multiple of the block size.
Base address register diagrams show how base register bits correspond to address
lines.
This field determines the size of the block that is enabled by the chip-select.
Table D-13 shows bit encoding for the base address registers block size field.
DATA7
ADDR
ADDR
14
22
14
22
1
1
1
1
1
0
0
0
ADDR
ADDR
13
21
13
21
DATA6
0
0
Data Bus Pins at Reset
X
1
1
1
1
0
ADDR
ADDR
12
20
12
20
0
0
DATA5
Table D-12 Reset Pin Function of CS[10:6]
ADDR
ADDR
X
X
1
1
1
0
11
19
11
19
0
0
ADDR
ADDR
DATA4
10
18
10
18
0
0
X
X
X
1
1
0
ADDR
ADDR
REGISTER SUMMARY
17
17
9
0
9
0
DATA3
X
X
X
X
1
0
ADDR
ADDR
16
16
8
0
8
0
ADDR23
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
ADDR
ADDR
CS10/
CS10
CS10
CS10
CS10
CS10
15
15
7
0
7
0
Chip-Select/Address Bus Pin Function
ADDR
ADDR
14
14
6
0
6
0
ADDR22
ADDR22 ADDR21 ADDR20 ADDR19
CS9/
CS9
CS9
CS9
CS9
ADDR
ADDR
13
13
5
0
5
0
ADDR21
ADDR21 ADDR20 ADDR19
ADDR
ADDR
CS8/
CS8
CS8
CS8
12
12
4
0
4
0
$YFFA4C–$YFFA74
ADDR
ADDR
11
11
3
0
3
0
ADDR20
ADDR20 ADDR19
CS7/
CS7
CS7
2
1
2
0
ADDR19
ADDR19
BLKSZ[2:0]
BLKSZ[2:0]
$YFFA48
MOTOROLA
CS8/
CS6
1
1
1
0
D-17
0
1
0
0