MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 67

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.8.2.3 Loop Mode Instruction Execution
4.9 Exception Processing
4.9.1 Exception Vectors
MC68336/376
USER’S MANUAL
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the perfor-
mance of the CPU32, a loop mode has been added to the processor. The loop mode
is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction. Figure 4-7 shows the
required form of an instruction loop for the processor to enter loop mode.
The loop mode is entered when the DBcc instruction is executed, and the loop dis-
placement is –4. Once in loop mode, the processor performs only the data cycles as-
sociated with the instruction and suppresses all instruction fetches. The termination
condition and count are checked after each execution of the data operations of the
looped instruction. The CPU32 automatically exits the loop mode on interrupts or other
exceptions. All single word instructions that do not cause a change of flow can be
looped.
An exception is a special condition that preempts normal processing. Exception pro-
cessing is the transition from normal mode program execution to execution of a routine
that deals with an exception.
An exception vector is the address of a routine that handles an exception. The vector
base register (VBR) contains the base address of a 1024-byte exception vector table,
which consists of 256 exception vectors. Sixty-four vectors are defined by the
processor, and 192 vectors are reserved for user definition as interrupt vectors. Except
for the reset vector, each vector in the table is one long word in length. The reset vector
is two long words in length. Refer to Table 4-3 for information on vector assignment.
Because there is no protection on the 64 processor-defined vectors,
external devices can access vectors reserved for internal purposes.
This practice is strongly discouraged.
Figure 4-7 Loop Mode Instruction Sequence
CENTRAL PROCESSOR UNIT
ONE WORD INSTRUCTION
DBCC DISPLACEMENT
$FFFC = – 4
DBCC
CAUTION
MOTOROLA
4-15
1126A