MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 69

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.9.2 Types of Exceptions
4.9.3 Exception Processing Sequence
4.10 Development Support
MC68336/376
USER’S MANUAL
An exception can be caused by internal or external events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause excep-
tions during normal execution. Illegal instructions, instruction fetches from odd ad-
dresses, word or long-word operand accesses from odd addresses, and privilege
violations also cause internal exceptions.
Sources of external exception include interrupts, breakpoints, bus errors, and reset re-
quests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access con-
trol and processor restart.
For all exceptions other than a reset exception, exception processing occurs in the fol-
lowing sequence. Refer to 5.7 Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the status
register. After the copy is made, the processor state bits in the status register are
changed — the S bit is set, establishing supervisor access level, and bits T1 and T0
are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority
mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from
CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions,
internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and
placed on the supervisor stack. All stack frames contain copies of the status register
and the program counter for use by RTE. The type of exception and the context in
which the exception occurs determine what other information is stored in the stack
frame.
Finally, the processor prepares to resume normal execution of instructions. The ex-
ception vector offset is determined by multiplying the vector number by four, and the
offset is added to the contents of the VBR to determine displacement into the excep-
tion vector table. The exception vector is loaded into the program counter. If no other
exception is pending, the processor will resume normal execution at the new address
in the PC.
The following features have been implemented on the CPU32 to enhance the instru-
mentation and development environment:
• M68000 Family Development Support
• Background Debug Mode
• Deterministic Opcode Tracking
• Hardware Breakpoints
CENTRAL PROCESSOR UNIT
MOTOROLA
4-17