MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 389

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

D.7.15 PWM Period Register
PWM5A1 — PWM5A Period Register
PWM6A1 — PWM6A Period Register
PWM7A1 — PWM7A Period Register
PWM8A1 — PWM8A Period Register
D.7.16 PWM Pulse Width Register
PWM5B1 — PWM5 Pulse Width Register
PWM6B1 — PWM6 Pulse Width Register
PWM7B1 — PWM7 Pulse Width Register
PWM8B1 — PWM8 Pulse Width Register
MC68336/376
USER’S MANUAL
15
15
U
U
RESET:
RESET:
The PWMA1 register contains the period value for the next cycle of the PWM output
waveform. When the PWMSM is enabled, a period value written to PWMA1 is loaded
into PWMA2 at the end of the current period or when the LOAD bit in PWMSIC is writ-
ten to one. If the PWMSM is disabled, a period value written to PWMA1 is loaded into
PWMA2 on the next half cycle of the MCU system clock. PWMA2 is a temporary reg-
ister that is used to smoothly update the PWM period value; it is not user-accessible.
The PWMSM hardware does not modify the contents of PWMA1 at any time.
14
14
U
U
13
13
U
U
CLK2
0
0
0
0
1
1
1
1
12
12
U
U
Table D-50 PWMSM Divide By Options
11
11
U
U
CLK1
0
0
1
1
0
0
1
1
10
10
U
U
CLK0
REGISTER SUMMARY
U
U
9
9
0
1
0
1
0
1
0
1
U
U
8
8
(CPCR DIV23 = 0)
PCLK1 = f
f
f
f
f
f
sys
sys
f
f
f
sys
sys
sys
sys
sys
sys
U
U
7
7
128
512
sys
16
32
64
2
4
8
U
U
6
6
2
U
U
5
5
(CPCR DIV23 = 0)
PCLK1 = f
f
f
f
f
f
f
sys
sys
f
f
sys
sys
sys
sys
4
U
4
U
sys
sys
192
768
sys
12
24
48
96
3
6
U
U
3
3
2
U
U
2
2
$YFF42A
$YFF43A
$YFF42C
$YFF43C
MOTOROLA
$YFF432
$YFF442
$YFF434
$YFF444
U
U
1
1
D-71
U
U
0
0