MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 351

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

QACR2 — Control Register 2
CIE2 — Queue 2 Completion Interrupt Enable
PIE2 — Queue 2 Pause Interrupt Enable
SSE2 — Queue 2 Single-Scan Enable Bit
MQ2[4:0] — Queue 2 Operating Mode
MC68336/376
USER’S MANUAL
RESET:
CIE2
15
0
CIE2 enables completion interrupts for queue 2. The interrupt request is generated
when the conversion is complete for the last CCW in queue 2.
PIE2 enables pause interrupts for queue 2. The interrupt request is generated when
the conversion is complete for a CCW that has the pause bit set.
SSE2 enables a single-scan of queue 2 after a trigger event occurs. The SSE2 bit may
be set to a one during the same write cycle that sets the MQ2[4:0] bits for the single-
scan queue operating mode. The single-scan enable bit can be written as a one or a
zero, but is always read as a zero.
The SSE2 bit allows a trigger event to initiate queue execution for any single-scan op-
eration on queue 2. The QADC clears SSE2 when the single-scan is complete.
The MQ2 field selects the queue operating mode for queue 2. Table D-26 shows the
bits in the MQ2 field which enable different queue 2 operating modes.
0 = Queue 2 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 2.
0 = Queue 2 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 2 which has
PIE2
14
0
the pause bit set.
SSE2
13
0
12
0
11
0
MQ2[4:0]
10
0
REGISTER SUMMARY
9
0
8
0
RES
7
0
USED
NOT
6
5
1
4
0
3
0
BQ2[5:0]
2
1
$YFF20E
MOTOROLA
1
1
D-33
0
1