MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 431

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

STOPACK D-87
STRB (address strobe/data strobe) bit 5-30, 5-60, D-19
STSIM 5-12, D-8
STUFFERR D-95
Submodule bus (SMB) 10-1
Subqueue 8-17
Substitute remote request (SRR) 13-5
Successive approximation register (SAR) 8-1, 8-16
Supervisor
SUPV 5-3, 8-8, D-29, D-41, D-87
SW D-9
SWE 5-15, D-12
SWP 5-16, D-12
SWSR D-14
SWT 5-16, D-12
Symbols 2-1
Synchronized pulse width modulation (SPWM) 11-7
SYNCR D-8
Synthesizer lock flag (SLOCK) D-8
SYPCR D-12
SYS D-9
SYSRST (system reset) 5-41
System
T D-3
T2CG 11-14, D-74
Table stepper motor (TSM) 11-10
TBB 10-1
TBL 4-14
TBRS1 D-58
TBRS2 D-58
TC 9-27, D-45
TCIE 9-27, D-44
TCR D-75
TCR1P 11-13, D-74
TCR2 clock/gate control (T2CG) D-74
TCR2P D-74
MC68336/376
USER’S MANUAL
SCI end of data frame bit 9-25
/unrestricted data space (SUPV)
stack pointer (SSP) 4-10
clock 5-4
frequencies 5-10
integration
memory maps. See Memory maps 3-14
protection control register (SYPCR) D-12
reset (SYS) D-9
SIM clock (STSIM) 5-12, D-8
CPU32 D-4
QADC D-29
QSM D-41
SIM 5-3, D-7
TouCAN D-87
TPU D-75
block diagram 5-4
output (CLKOUT) 5-26
sources 5-4
module. See SIM 5-1, D-5
test register - ECLK (SIMTRE) D-9
–T–
TDR 9-24
TDRE 9-27, D-45
TE D-44
Temporary register A (ATEMP) 4-20
Test
Thermal characteristics A-2
Three-state control (TSC) 5-49
TICR 11-13, D-77
TIE 9-27, D-44
Time
TIMER D-92
Timer
TOR1 D-35
TOR2 D-36
TouCAN
module
submodule
base
processor unit. See TPU 11-1
quanta clock 13-8
stamp 13-4, 13-10
count register
synchronize mode (TSYNC) D-90
address
bit timing configuration 13-8
block diagram 13-1
disable (FRZACK) D-87
external pins 13-2
features 3-3
function 13-1
initialization sequence 13-11
interrupts 13-19
message buffer address map D-85
not ready (NOTRDY) D-86
operation 13-3
receive process 13-13
registers
repetition count (TSTRC) D-21
shift count register (TSTSC) D-21
control register (CREG) D-21
reset (TST) D-9
bus driver for MCSM 10-9
buses (TBB) 10-1, 10-2
register bus select bits (TBRS1/0) D-58
1 prescaler control (TCR1P) D-74
2 prescaler control (TCR2P) D-74
map D-84
space 13-2
operation 13-9
control register 0 (CANCTRL0) D-88
control register 1 (CTRL1) 13-8
control register 1(CANCTRL1) D-90
control register 2 (CANCTRL2) D-91
control register 2 (CTRL2) 13-8
error and status register (ESTAT) D-94
free running timer register (TIMER) D-92
interrupt
allocation 10-3
configuration register (CANICR) D-88
flag register (IFLAG) D-96
MOTOROLA
I-15