MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 238

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

11.3.1 Event Timing
11.3.2 Channel Orthogonality
11.3.3 Interchannel Communication
11.3.4 Programmable Channel Service Priority
11.3.5 Coherency
11-4
MOTOROLA
When a match or input capture event requiring service occurs, the affected channel
generates a service request to the scheduler. The scheduler determines the priority of
the request and assigns the channel to the microengine at the first available time. The
microengine performs the function defined by the content of the control store or emu-
lation RAM, using parameters from the parameter RAM.
Match and capture events are handled by independent channel hardware. This pro-
vides an event accuracy of one time-base clock period, regardless of the number of
channels that are active. An event normally causes a channel to request service. The
time needed to respond to and service an event is determined by which channels and
the number of channels requesting service, the relative priorities of the channels re-
questing service, and the microcode execution time of the active functions. Worst-
case event service time (latency) determines TPU performance in a given application.
Latency can be closely estimated. For more information, refer to the TPU Reference
Manual (TPURM/AD)
Most timer systems are limited by the fixed number of functions assigned to each pin.
All TPU channels contain identical hardware and are functionally equivalent in opera-
tion, so that any channel can be configured to perform any time function. Any function
can operate on the calling channel, and, under program control, on another channel
determined by the program or by a parameter. The user controls the combination of
time functions.
The autonomy of the TPU is enhanced by the ability of a channel to affect the opera-
tion of one or more other channels without CPU32 intervention. Interchannel commu-
nication can be accomplished by issuing a link service request to another channel, by
controlling another channel directly, or by accessing the parameter RAM of another
channel.
The TPU provides a programmable service priority level to each channel. Three prior-
ity levels are available. When more than one channel of a given priority requests ser-
vice at the same time, arbitration is accomplished according to channel number. To
prevent a single high-priority channel from permanently blocking other functions, other
service requests of the same priority are performed in channel order after the lowest-
numbered, highest-priority channel is serviced.
For data to be coherent, all available portions of the data must be identical in age, or
must be logically related. As an example, consider a 32-bit counter value that is read
and written as two 16-bit words. The 32-bit value is read-coherent only if both 16-bit
portions are updated at the same time, and write-coherent only if both portions take
TIME PROCESSOR UNIT
USER’S MANUAL
MC68336/376