MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 62

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.7 Privilege Levels
4.8 Instructions
4-10
MOTOROLA
CALLM, RTM
PACK, UNPK
CAS, CAS2
The exception processing state is associated with interrupts, trap instructions, tracing,
and other exception conditions. The exception may be internally generated explicitly
by an instruction or by an unusual condition arising during the execution of an instruc-
tion. Exception processing can be forced externally by an interrupt, a bus error, or a
reset.
The halted processing state is an indication of catastrophic hardware failure. For ex-
ample, if during the exception processing of a bus error another bus error occurs, the
processor assumes that the system is unusable and halts.
The background processing state is initiated by breakpoints, execution of special in-
structions, or a double bus fault. Background processing is enabled by pulling BKPT
low during RESET. Background processing allows interactive debugging of the sys-
tem via a simple serial interface.
The processor operates at one of two levels of privilege: user or supervisor. Not all in-
structions are permitted to execute at the user level, but all instructions are available
at the supervisor level. Effective use of privilege level can protect system resources
from uncontrolled access. The state of the S bit in the status register determines the
privilege level and whether the user stack pointer (USP) or supervisor stack pointer
(SSP) is used for stack operations.
The CPU32 instruction set is summarized in Table 4-2. The instruction set of the
CPU32 is very similar to that of the MC68020. Two new instructions have been added
to facilitate controller applications: low-power stop (LPSTOP) and table lookup and in-
terpolate (TBLS, TBLSN, TBLU, TBLUN).
Table 4-1 shows the MC68020 instructions that are not implemented on the CPU32.
The CPU32 traps on unimplemented instructions or illegal effective addressing
modes, allowing user-supplied code to emulate unimplemented capabilities or to de-
fine special purpose functions. However, Motorola reserves the right to use all current-
ly unimplemented instruction operation codes for future M68000 core enhancements.
Memory
cpxxx
BFxx
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST)
— Call Module, Return Module
— Compare and Swap (Read-Modify-Write Instructions)
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN)
— Pack, Unpack BCD Instructions
— Memory Indirect Addressing Modes
Table 4-1 Unimplemented MC68020 Instructions
CENTRAL PROCESSOR UNIT
USER’S MANUAL
MC68336/376