MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 395

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

CHBK — Channel Register Breakpoint Flag
SRBK — Service Request Breakpoint Flag
TPUF — TPU FREEZE Flag
D.8.5 TPU Interrupt Configuration Register
TICR — TPU Interrupt Configuration Register
CIRL[2:0] — Channel Interrupt Request Level
CIBV[3:0] — Channel Interrupt Base Vector
D.8.6 Channel Interrupt Enable Register
CIER — Channel Interrupt Enable Register
CH[15:0] — Channel Interrupt Enable/Disable
MC68336/376
USER’S MANUAL
CH 15
15
15
0
RESET:
RESET:
CHBK is asserted if a breakpoint occurs because of a CHAN register match with the
CHAN register breakpoint register. CHBK is negated when the BKPT flag is cleared.
SRBK is asserted if a breakpoint occurs because of any of the service request latches
being asserted along with their corresponding enable flag in the development support
control register. SRBK is negated when the BKPT flag is cleared.
TPUF is set whenever the TPU is in a halted state as a result of FREEZE being as-
serted. This flag is automatically negated when the TPU exits the halted state because
of FREEZE being negated.
This three-bit field specifies the interrupt request level for all channels. Level seven for
this field indicates a non-maskable interrupt; level zero indicates that all channel inter-
rupts are disabled.
The TPU is assigned 16 unique interrupt vector numbers, one vector number for each
channel. The CIBV field specifies the most significant nibble of all 16 TPU channel in-
terrupt vector numbers. The lower nibble of the TPU interrupt vector number is deter-
mined by the channel number on which the interrupt occurs.
CH 14
0 = Channel interrupts disabled
1 = Channel interrupts enabled
14
0
NOT USED
CH 13
13
0
CH 12
12
0
CH 11
11
0
CH 10
10
10
0
0
CIRL[2:0]
REGISTER SUMMARY
CH 9
9
0
9
0
CH 8
8
0
8
0
CH 7
7
0
7
0
CH 6
6
0
6
0
CIBV[3:0]
CH 5
5
0
5
0
CH 4
4
0
4
0
CH 3
3
3
0
CH 2
NOT USED
2
0
$YFFE0A
$YFFE08
MOTOROLA
CH 1
1
0
CH 0
D-77
0
0
0