MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 220

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

10.4.3 LPSTOP Effect on the BIUSM
10.4.4 BIUSM Registers
10.5 Counter Prescaler Submodule (CPSM)
10-4
MOTOROLA
If the IMB FREEZE signal is asserted and FRZ = 0, the freeze condition is ignored,
and all CTM4 submodules will continue to operate normally.
When the CPU32 LPSTOP instruction is executed, the system clock is stopped. All de-
pendent modules, including the CTM4, are shut down until low-power STOP mode is
exited.
The BIUSM contains a module configuration register, a time base register, and a test
register. The BIUSM register block occupies the first four register locations in the
CTM4 register space. All unused bits and reserved address locations return zero when
read. Writes to unused bits and reserved address locations have no effect. Refer to
D.7.1 BIU Module Configuration Register, D.7.2 BIUSM Test Configuration Reg-
ister, and D.7.3 BIUSM Time Base Register for information concerning BIUSM reg-
ister and bit descriptions.
The counter prescaler submodule (CPSM) is a programmable divider system that pro-
vides the CTM4 counters with a choice of six clock signals (PCLK[1:6]) derived from
the main MCU system clock. Five of these frequencies are derived from a fixed divider
chain. The divide ratio of the last clock frequency is software selectable from a choice
of four divide ratios.
The CPSM is part of the BIUSM. Figure 10-2 shows a block diagram of the CPSM.
• The state of the PWMSM output flip-flop will remain unchanged.
output flip-flop will remain unchanged.
f
sys
FIRST CPSM
PRESCALER
2 OR 3
Figure 10-2 CPSM Block Diagram
CONFIGURABLE TIMER MODULE 4
PRESCALER
8-BIT
PRUN DIV23 PSEL1 PSEL0
128
256
16
32
64
2
4
8
SELECT
CPCR
PCLK1 =
PCLK2 =
PCLK3 =
PCLK4 =
PCLK5 =
PCLK6 =
DIV23 = 2
f
f
f
sys
sys
f
f
f
sys
f
f
f
sys
sys
sys
sys
sys
sys
512
128
256
16
32
64
2
4
8
DIV23 = 3
f
f
f
f
sys
f
f
f
sys
sys
sys
f
f
sys
sys
sys
sys
sys
384
768
192
12
24
48
96
3
6
USER’S MANUAL
MC68336/376
CTM CPSM BLOCK