MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 391

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

D.8 Time Processor Unit (TPU)
D.8.1 TPU Module Configuration Register
TPUMCR — TPU Module Configuration Register
STOP — Low-Power Stop Mode Enable
MC68336/376
USER’S MANUAL
STOP
15
0
RESET:
Table D-51 shows the TPU address map. The column labeled “Access” indicates the
privilege level at which the CPU32 must be operating to access the register. A
designation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or
unrestricted access.
NOTES:
Access
0 = Enable TPU clocks.
1 = Disable TPU clocks.
14
TCR1P[1:0]
0
S/U
S/U
S/U
S/U
1. Y = M111, where M represents the logic state of the module mapping (MM) bit in the SIMCR.
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
13
0
Address
$YFFE0A
$YFFE0C
$YFFE0E
$YFFE1A
$YFFE1C
$YFFE1E
$YFFE00
$YFFE02
$YFFE04
$YFFE06
$YFFE08
$YFFE10
$YFFE12
$YFFE14
$YFFE16
$YFFE18
$YFFE20
$YFFE22
$YFFE24
$YFFE26
12
TCR2P[1:0]
0
1
11
0
15
Table D-51 TPU Register Map
EMU
10
0
T2CG
REGISTER SUMMARY
9
0
Channel Function Selection Register 0 (CFSR0)
Channel Function Selection Register 1 (CFSR1)
Channel Function Selection Register 2 (CFSR2)
Channel Function Selection Register 3 (CFSR3)
Development Support Control Register (DSCR)
Development Support Status Register (DSSR)
Decoded Channel Number Register (DCNR)
TPU Interrupt Configuration Register (TICR)
Host Service Request Register 0 (HSRR0)
Module Configuration Register (TPUMCR)
Host Service Request Register 1 (HSRR1)
Channel Interrupt Enable Register (CIER)
Channel Interrupt Status Register (CISR)
Service Grant Latch Register (SGLR)
STF
Host Sequence Register 0 (HSQR0)
Host Sequence Register 1 (HSQR1)
Channel Priority Register 0 (CPR0)
8
0
Test Configuration Register (TCR)
Channel Priority Register 1 (CPR1)
SUPV
7
1
Link Register (LR)
PSCK
6
0
5
0
0
4
0
0
3
0
2
0
IARB[3:0]
$YFFE00
MOTOROLA
0
1
0
D-73
0
0