MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 326

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

D.2.3 Clock Synthesizer Control Register
SYNCR — Clock Synthesizer Control Register
W — Frequency Control (VCO)
X — Frequency Control (Prescaler)
Y[5:0] — Frequency Control (Counter)
EDIV — E Clock Divide Rate
SLOCK — Synthesizer Lock Flag
STSIM — Stop Mode SIM Clock
D-8
MOTOROLA
NOTES:
15
W
0
RESET:
1. Ensure that initialization software does not change the value of these bits. They should always be zero.
SYNCR determines system clock operating frequency and operation during low-power
stop mode. Clock frequency is determined by SYNCR bit settings as follows:
This bit controls a prescaler tap in the synthesizer feedback loop. Setting this bit
increases the VCO speed by a factor of four. VCO relock delay is required.
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop.
Setting the bit doubles clock speed without changing the VCO speed. No VCO relock
delay is required.
The Y field controls the modulus down counter in the synthesizer feedback loop, caus-
ing it to divide by a value of Y + 1. VCO relock delay is required.
ECLK is an external M6800 bus clock available on ADDR23.
The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate
synthesizer lock status until after the user writes to SYNCR.
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or VCO is disabled.
0 = When LPSTOP is executed, the SIM clock is driven from the crystal oscillator
1 = When LPSTOP is executed, the SIM clock is driven from the VCO.
14
X
0
and the VCO is turned off to conserve power.
13
1
12
1
11
1
Y[5:0]
10
1
f
sys
9
1
REGISTER SUMMARY
=
--------- - 4 Y
128
8
1
f
ref
EDIV
7
0
+
1
6
0
0
2
2W
5
0
0
+
X
RSVD
4
0
1
SLOCK RSVD
U
3
USER’S MANUAL
2
0
1
MC68336/376
$YFFA04
STSIM
1
0
STEXT
0
0