MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 214

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

8.13 Interrupts
8.13.1 Interrupt Sources
8.13.2 Interrupt Register
8-32
MOTOROLA
The QADC supports both polled and interrupt driven operation. Status bits in QASR
reflect the operating condition of each queue and can optionally generate interrupts
when enabled by the appropriate bits in QACR1 and/or QACR2.
The QADC has four interrupt service sources, each of which is separately enabled.
Each time the result is written for the last CCW in a queue, the completion flag for the
corresponding queue is set, and when enabled, an interrupt request is generated. In
the same way, each time the result is written for a CCW with the pause bit set, the
queue pause flag is set, and when enabled, an interrupt request is generated.
Table 8-5 displays the status flag and interrupt enable bits which correspond to queue
1 and queue 2 activity.
Both polled and interrupt-driven QADC operations require that status flags must be
cleared after an event occurs. Flags are cleared by first reading QASR with the appro-
priate flag bits set to one, then writing zeros to the flags that are to be cleared. A flag
can be cleared only if the flag was a logic one at the time the register was read by the
CPU. If a new event occurs between the time that the register is read and the time that
it is written, the associated flag is not cleared.
The QADC interrupt register QADCINT specifies the priority level of QADC interrupt
requests and the upper six bits of the vector number provided during an interrupt ac-
knowledge cycle.
The values contained in the IRLQ1 and IRLQ2 fields in QADCINT determine the pri-
ority of QADC interrupt service requests. A value of %000 in either field disables the
interrupts associated with that field. The interrupt levels for queue 1 and queue 2 may
be different.
The IVB[7:2] bits specify the upper six bits of each QADC interrupt vector number.
IVB[1:0] have fixed assignments for each of the four QADC interrupt sources. Refer to
8.13.3 Interrupt Vectors for more information.
Queue 1
Queue 2
Queue
Result written for the last CCW in queue 1
Result written for a CCW with pause bit set in
queue 1
Result written for the last CCW in queue 2
Result written for a CCW with pause bit set in
queue 2
Table 8-5 QADC Status Flags and Interrupt Sources
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
Queue Activity
Status Flag
CF1
PF1
CF2
PF2
Interrupt Enable Bit
USER’S MANUAL
CIE1
CIE2
PIE1
PIE2
MC68336/376