MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 393

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

STF — Stop Flag
SUPV — Supervisor/Unrestricted
PSCK — Prescaler Clock
IARB[3:0] — Interrupt Arbitration ID
D.8.2 Test Configuration Register
TCR — Test Configuration Register
D.8.3 Development Support Control Register
DSCR — Development Support Control Register
HOT4 — Hang on T4
BLC — Branch Latch Control
CLKS — Stop Clocks (to TCRs)
FRZ[1:0] — FREEZE Assertion Response
MC68336/376
USER’S MANUAL
HOT4
15
0
RESET:
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
Used for factory test only.
The FRZ bits specify the TPU microengine response to the IMB FREEZE signal. Refer
to Table D-54.
0 = TPU is operating.
1 = TPU is stopped (STOP bit has been set).
0 = Assignable registers are accessible in user or supervisor mode.
1 = Assignable registers are accessible in supervisor mode only.
0 = f
1 = f
0 = Exit wait on T4 state caused by assertion of HOT4.
1 = Enter wait on T4 state.
0 = Latch conditions into branch condition register before exiting halted state.
1 = Do not latch conditions into branch condition register before exiting the halted
0 = Do not stop TCRs.
1 = Stop TCRs during the halted state.
14
state or during the time-slot transition period.
sys
sys
13
NOT USED
32 is input to TCR1 prescaler.
4 is input to TCR1 prescaler.
12
11
BLC
10
0
REGISTER SUMMARY
CLKS
9
0
8
0
FRZ[1:0]
7
0
CCL
6
0
BP
5
0
BC
4
0
BH
3
0
BL
2
0
$YFFE02
$YFFE04
MOTOROLA
BM
1
0
D-75
BT
0
0