MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 429

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

RTE 5-36
RTR 13-4, 13-5, 13-15
RWU 9-29, D-44
RX
RX14MSKHI D-93
RX14MSKLO D-93
RX15MSKHI D-93
RX15MSKLO D-93
RXD 9-24
RXECTR D-97
RXGMSKHI D-93
RXGMSKLO D-93
RXMODE D-89
RXWARN D-95
S D-4
SAMP D-90
Sample amplifier bypass (BYP) D-37
Sampling mode (SAMP) D-90
SAR 8-1, 8-16
SASM
SBK 9-27, D-44
Scan modes
SCBR D-43
SCCR 9-21
SCCR0 D-42
SCCR1 D-43
SCDR 9-24, D-46
SCI 9-1, 9-2, 9-16, 9-21
SCK 9-16, 9-19
S-clock 13-8
SCSR 9-24, D-45
Self wake enable (SELFWAKE) D-87
Send break (SBK) 9-27, D-44
MC68336/376
USER’S MANUAL
Length 13-4
timing (electricals) A-32
baud
idle-line detection 9-28
internal loop 9-30
operation 9-24
parity checking 9-26
pins 9-24
receiver
registers 9-21
transmitter
actual delay before SCK (equation) 9-17
baud rate (equation) 9-17
clock 9-25
rate (SCBR) D-43
block diagram 9-23
operation 9-28
wakeup 9-29
control registers (SCCR) 9-21
data register (SCDR) 9-24
status register (SCSR) 9-24
block diagram 9-22
operation 9-26
equation D-43
–S–
Serial
Service
Set (definition) 2-8
SFC 4-7
SGLR D-80
SHEN 5-39, D-7
Show cycle
Signal
Signature registers (RSIGHI/LO) 7-1
SIM 5-1
clock baud rate (SPBR) D-49
communication interface (SCI) 9-1, 9-21
formats 9-25
interface 4-23
mode (M) bit 9-25
shifter 9-24, 9-26
request breakpoint flag (SRBK) D-77
enable (SHEN) 5-3, 5-39, D-7
operation 5-39
timing diagram A-17
characteristics 3-9
functions 3-11
address map D-5
block diagram 5-2
bus operation 5-26
chip-selects 5-54
external bus interface (EBI) 5-19
features 3-1
functional blocks 5-1
halt monitor 5-15
interrupt arbitration 5-3
interrupts 5-50
low-power stop operation 5-19
module configuration register (SIMCR) D-6
parallel I/O ports 5-64
periodic interrupt timer 5-17
register access 5-3
registers
block diagram (with software watchdog) 5-17
chip-select
clock synthesizer control register (SYNCR) D-8
distributed register (DREG) D-21
master shift register A/B (TSTMSRA/B) D-21
module configuration register (SIMCR) 5-2
periodic interrupt
port C data register (PORTC) 5-60, D-15
port E
base address
option
pin assignment registers (CSPAR) 5-57,
control register (PICR) D-13
timer register (PITR) 5-17, D-14
data direction register (DDRE) 5-64, D-10
data register (PORTE) 5-64, D-10
pin assignment register (PEPAR) 5-64,
register boot ROM (CSBARBT) D-17
registers (CSBAR) 5-57, 5-58, D-17
register boot ROM (CSORBT) D-18
registers (CSOR) 5-57, 5-59, D-18
D-15
MOTOROLA
I-13