MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 58

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.2.3 Program Counter
4.2.4 Control Registers
4.2.4.1 Status Register
4-6
MOTOROLA
The PC contains the address of the next instruction to be executed by the CPU32.
During instruction execution and exception processing, the processor automatically
increments the contents of the PC or places a new value in the PC as appropriate.
The control registers described in this section contain control information for supervi-
sor functions and vary in size. With the exception of the condition code register (the
user portion of the status register), they are accessed only by instructions at the su-
pervisor privilege level.
The status register (SR) stores the processor status. It contains the condition codes
that reflect the results of a previous operation and can be used for conditional instruc-
tion execution in a program. The condition codes are extend (X), negative (N), zero
(Z), overflow (V), and carry (C). The user (low-order) byte containing the condition
codes is the only portion of the SR information available at the user privilege level; it
is referenced as the condition code register (CCR) in user programs.
At the supervisor privilege level, software can access the full status register. The upper
byte of this register includes the interrupt priority (IP) mask (three bits), two bits for
placing the processor in one of two tracing modes or disabling tracing, and the super-
visor/user bit for placing the processor at the desired privilege level.
Undefined bits in the status register are reserved by Motorola for future definition. The
undefined bits are read as zeros and should be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations, but for all CCR operations,
the upper byte is read as all zeros and is ignored when written, regardless of privilege
level.
Refer to D.1.2 Status Register for bit/field definitions and a diagram of the status reg-
ister.
31
31
Figure 4-5 Address Organization in Address Registers
SIGN EXTENDED
FULL 32-BIT ADDRESS OPERAND
CENTRAL PROCESSOR UNIT
16 15
16-BIT ADDRESS OPERAND
USER’S MANUAL
0
0
CPU32 ADDR ORG
MC68336/376