MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 360

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

ILQSPI[2:0] — Interrupt Level for QSPI
ILSCI[2:0] — Interrupt Level for SCI
D.6.4 QSM Interrupt Vector Register
QIVR — QSM Interrupt Vector Register
INTV[7:0] — Interrupt Vector Number
D.6.5 SCI Control Register
SCCR0 — SCI Control Register 0
Bits [15:13] — Not Implemented
D-42
MOTOROLA
RESET:
15
15
0
RESET:
When an interrupt request is made, ILQSPI value determines which of the interrupt
request signals is asserted; when a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond.
ILQSPI must have a value in the range $0 (interrupts disabled) to $7 (highest priority).
When an interrupt request is made, ILSCI value determines which of the interrupt
request signals is asserted. When a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. The
field must have a value in the range $0 (interrupts disabled) to $7 (highest priority).
If ILQSPI[2:0] and ILSCI[2:0] have the same non-zero value, and both submodules
simultaneously request interrupt service, the QSPI has priority.
QIVR determines the value of the interrupt vector number the QSM supplies when it
responds to an interrupt acknowledge cycle. At reset, QIVR is initialized to $0F, the
uninitialized interrupt vector number. To use interrupt-driven serial communication, a
user-defined vector number must be written to QIVR.
The values of INTV[7:1] are the same for both QSPI and SCI interrupt requests; the
value of INTV0 used during an interrupt acknowledge cycle is supplied by the QSM.
INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI
interrupt. A write to INTV0 has no effect. Reads of INTV0 return a value of one.
SCCR0 contains the SCI baud rate selection field. Baud rate must be set before the
SCI is enabled. The CPU32 can read and write SCCR0 at any time. Changing the
value of SCCR0 bits during a transfer operation can disrupt the transfer.
NOT USED
14
0
13
13
0
12
12
0
QILR
11
11
0
10
10
0
REGISTER SUMMARY
9
9
0
8
8
0
7
0
7
0
SCBR[12:0]
6
0
6
0
5
0
5
0
4
0
4
0
INTV[7:0]
3
1
3
0
USER’S MANUAL
2
1
2
1
MC68336/376
$YFFC05
$YFFC08
1
1
1
0
0
1
0
0