TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 107

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

31-28
27-26
25-24
23-5
4
3-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
7.6.2.6
−
SETENA
−
SETENA
−
SETENA
Bit Symbol
(Interrupt 55)
(Interrupt 47)
(Interrupt 39)
SETENA
SETENA
SETENA
Interrupt Set-Enable Register 2
Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources".
31
23
15
0
0
0
7
0
-
R/W
R/W
R/W
R/W
R/W
R/W
Type
(Interrupt 54)
(Interrupt 46)
(Interrupt 38)
SETENA
SETENA
SETENA
30
22
14
0
0
0
6
0
Write as 0.
Interrupt number [59:58]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
Write as 0.
Interrupt number [55:37]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
Write as 0.
Interrupt number [35:32]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
-
(Interrupt 53)
(Interrupt 45)
(Interrupt 37)
SETENA
SETENA
SETENA
29
21
13
0
0
0
5
0
-
(Interrupt 52)
(Interrupt 44)
Page 83
SETENA
SETENA
28
20
12
0
0
0
4
0
-
-
(Interrupt 59)
(Interrupt 51)
(Interrupt 43)
(Interrupt 35)
SETENA
SETENA
SETENA
SETENA
27
19
11
Function
0
0
0
3
0
(Interrupt 58)
(Interrupt 50)
(Interrupt 42)
(Interrupt 34)
SETENA
SETENA
SETENA
SETENA
26
18
10
0
0
0
2
0
(Interrupt 49)
(Interrupt 41)
(Interrupt 33)
SETENA
SETENA
SETENA
25
17
0
0
9
0
1
0
-
TMPM361F10FG
(Interrupt 48)
(Interrupt 40)
(Interrupt 32)
SETENA
SETENA
SETENA
24
16
0
0
8
0
0
0
-