TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 113

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TMPM361F10FG

Manufacturer Part Number
TMPM361F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM361F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Contact Us
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14Ã?14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
3
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM361F10FG
Manufacturer:
Toshiba
Quantity:
10 000
31-24
23-16
15-14
13-10
9-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
7.6.2.11
Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources".
CLRENA
CLRENA
Bit Symbol
(Interrupt 87)
CLRENA
Interrupt Clear-Enable Register 3
31
23
15
0
0
0
7
0
-
-
-
R/W
R/W
R/W
R/W
R/W
Type
(Interrupt 86)
CLRENA
30
22
14
0
0
0
6
0
Write as 0.
Interrupt number [87:80]
[Write]
1: Disabled
[Read]
0: Disabled
1: Enable
Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to
check if interrupts are disabled.
Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
Write as 0.
Interrupt number [77:74]
[Write]
1: Disabled
[Read]
0: Disabled
1: Enable
Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to
check if interrupts are disabled.
Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
Write as 0.
-
-
-
(Interrupt 85)
(Interrupt 77)
CLRENA
CLRENA
29
21
13
0
0
0
5
0
-
-
(Interrupt 84)
(Interrupt 76)
Page 89
CLRENA
CLRENA
28
20
12
0
0
0
4
0
-
-
(Interrupt 83)
(Interrupt 75)
CLRENA
CLRENA
27
19
11
Function
0
0
0
3
0
-
-
(Interrupt 82)
(Interrupt 74)
CLRENA
CLRENA
26
18
10
0
0
0
2
0
-
-
(Interrupt 81)
CLRENA
25
17
0
0
9
0
1
0
-
-
-
TMPM361F10FG
(Interrupt 80)
CLRENA
24
16
0
0
8
0
0
0
-
-
-

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