TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 424

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13.6
Frame Format
13.6
starting from the MSB.
Each frame format is between 4 and 16 bits wide depending on the size of data programmed, and is transmitted
Refer to Section "13.6.1" to "13.6.3" for details of each frame format.
Frame Format
・ Serial clock (SPCLK)
・ Serial frame (SPFSS)
SSP is in the idle state. In addition, data is output at the set bit rate only during data transmission.
during frame transmission.
this frame format, output data is transmitted at the rising edge of SPCLK and the input data is received
at its falling edge.
Signals remain "Low" in the SSI and Microwire formats and as inactive in the SPI format while the
In the SPI and Microwire frame formats, signals are set to "Low" active and always asserted to "Low"
In the SSI frame format, signals are asserted only during 1 bit rate before each frame transmission. In
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