TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 78

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

6.6
Low Power Consumption Modes
Table 6-8 Release Source in Each Mode
Release
source
ο :
× :
Starts the interrupt handling after the mode is released. (The reset initializes the LSI)
Unavailable
NMI (INTWDT)
NMI (NMI pin)
RESET (RESET pin)
Interrupt
Note 1: Refer to "6.6.8 Warm-up" about warm-up time.
Note 2: After releasing BACKUP mode, initialize the circuit except BACKUP module.
Note 3: To release the low power consumption mode by using the level mode interrupt, keep the level until the interrupt han-
Note 4: For shifting to the low power consumption mode, set the CPU to prohibit all the interrupts other than the release
Note 5: INTCECRX (CEC reception interrupt) is source trigger for wake up in the BACKUP SLEEP mode. INTCECTX
Note 6: To shift from NORMAL mode to IDLE1 mode, Warm-up time requires more than 100μs. If not, recovery time of
Refer to "Interrupts" for detail.
Low power consumption mode
・ Release by interrupt request
・ Release by Non-Maskable Interrupt (NMI)
・ Release by reset
INT0 to 4, E, F (note 3)
INT5 to INT7 (note 3)
INTRTC
INTTB0 to F
INTCAP10 to 20,50 to 70, 90
INTCAP 11 to 21,51 to 71,91
INTRX0 to 4, INTTX0 to 4
INTSBI0 to 3
INTCECRX, INTCECTX
INTRMCRX0
INTAD / INTADHP / INTADM0, 1
INTKWUP
dling is started. Changing the level before then will prevent the interrupt handling from starting properly.
source. If not, releasing may be executed by an unspecified for wake up.
(CEC transmission interrupt) is not trigger for wake up in the BACKUP SLEEP mode.
MCU internal system is not done when the return from IDLE1 mode.
tect the interrupt. In addition to the setting in the CPU, the clock generator must be set to detect
the interrupt to be used to release the SLEEP and STOP modes.
ly be used in the IDLE2 mode. The NMI pin can be used to release all the lower power consump-
tion modes except BACKUP and IDLE1 mode.
mode switches to the NORMAL mode and all the registers are initialized as is the case with nor-
mal reset.
the reset signal valid until the oscillator operation becomes stable.
To release the low power consumption mode by an interrupt, the CPU must be set in advance to de-
There are two kinds of NMI sources: WDT interrupt (INTWDT) and NMI pin. INTWDT can on-
Any low power consumption mode can be released by reset from the RESET pin. After that, the
Note that releasing from the STOP mode by reset does not induce the automatic warm-up. Keep
IDLE2
Page 54
ο
ο
ο
ο
ο
ο
ο
ο
ο
ο
ο
ο
ο
ο
ο
(note 1)
IDLE1
ο
ο
ο
×
×
×
×
×
ο
ο
×
ο
×
×
ο
SLEEP
ο
ο
ο
×
×
×
×
×
ο
ο
×
ο
×
ο
ο
STOP
ο
ο
×
×
×
×
×
×
×
×
×
ο
×
ο
ο
TMPM361F10FG
ο (note 5)
BACKUP
(note 2)
SLEEP
ο
×
ο
×
×
×
×
×
ο
×
ο
×
×
ο
BACKUP
(note 2)
STOP
ο
×
×
×
×
×
×
×
×
×
×
ο
×
×
ο