TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 41

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

2.4
2.5
2.6
struction execution. If an event is input, the core returns from low-power consumption mode caused by WFE instruc-
tion.
and WFE instruction.
nals. SLEEPDEEP signals are output when <SLEEPDEEP> bit of System Control Register is set.
event signals are not used so that please do not use WFE instruction.
this function.
Events
The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV in-
TMPM361F10FG does not use event output signals and event input signals. Please do not use SEV instruction
Power Management
The Cortex-M3 core provides power management system which uses SLEEPING signals and SLEEPDEEP sig-
These signals are output in the following circumstances:
TMPM361F10FG does not use SLEEPDEEP signals so that <SLEEPDEEP> bit must not be set. And also
For detail of power management, refer to the Chapter "Clock/Mode control."
Exclusive access
In Cortex-M3 core, the DCode bus system supports exclusive access. However, TMPM361F10FG does not use
-
-
-
Wait-For-Interrupt (WFI) instruction execution
Wait-For-Event (WFE) instruction execution
the timing when interrupt-service-routine (ISR) exit in case that <SLEEPONEXIT> bit of System Con-
trol Register is set.
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TMPM361F10FG