TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 389

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.14
12.14.1
12.14.1.1
12.14.1.2
RXD
Interrupt / Error Generation Timing
Figure 12-10 shows the data flow of receive operation and the route of read.
which are given follows.
SCxRFC<RFIS> setting are established.
Table 12-13 Receive Interrupt Conditions in use of FIFO
RX Interrupt
RX interrupts are generated at the time depends on the transfer mode and the buffer configurations,
In use of FIFO, receive interrupt is generated on the condition that the following either operation and
Interrupt conditions are decided by the SCxRFC<RFIS> settings as described in Table 12-13.
Buffer Configuration
Note:Interrupts are not generated when an overrun error occurs.
SCxRFC<RFIS>
If the receive buffer is emply,
Double Buffer
Single Buffer
Single Buffer / Double Buffer
FIFO
If the RX FIFO is not full,
Figure 12-10 Receive Buffer / FIFO Configuration Diagram
・ Reception completion of all bits of one frame
・ Reading FIFO
"0"
"1"
the data is moved.
the data is moved.
Receive FIFO First stage
"The fill level of FIFO" is greater than or equal to "the fill level of FIFO interruption generation."
−
Around the center of the first stop bit
Receive shift register
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
Receive buffer
UART modes
second stage
Third stage
Fourth stage
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Interrupt conditions
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
On data transfer from the shift register to the buffer by reading buffer.
(1)Reading in the single buffer configuration :
(2)Reading in the doule buffer configuration :
(3)Reading in use the FIFO :
An interrupt is generated after receiving all bits.
An interrupt is generated when the data is moved to
the receive buffer.
An interrupt is generated
When the data is moved to the FIFO
or when reading the FIFO.
I/O interface modes
TMPM361F10FG