TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 74

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

6.6
Low Power Consumption Modes
6.6.2
6.6.3
6.6.4
Table 6-5 Pin States in the STOP mode
ο : Input or output enabled.
× : Input or output disabled.
Port
port
Not
eration.
tion.
pin status in the STOP mode.
more details, refer to the BACKUP module.
SLEEP mode
STOP mode
BACKUP mode (BACKUP STOP, BACKUP SLEEP)
In the SLEEP mode, the internal low-speed oscillator, real time clock, CEC and RMC can be operated.
By releasing the SLEEP mode, the device returns to the preceding mode of the SLEEP mode and starts op-
All the internal circuits including the internal oscillator are brought to a stop in the STOP mode.
By releasing the STOP mode, the device returns to the preceding mode of the STOP mode and starts opera-
The STOP mode enables to select the pin status by setting the CGSTBYCR<DRVE>. Table 6-5 shows the
BACKUP mode realizes the lowest power consumption by cutting off the internal power regulator.About
X1, XT1
X2, XT2
RESET, NMI, MODE
PL3, PL7, PM3, PM7, PN3, PE7, PG3,
PG7, PI2, PI3
[When used as interrupt pin
(PxFRn<PxmFn>=1) and input is enabled
(PxIE<PxmIE>=1)]) (note)
PJ4,PJ5, PJ6, PJ7
(When used as KWUP pin
(PxFRn<PxmFn>=1) and input is enabled
(PxIE<PxmIE>=1)] (note)
PF0, PF1, PF2, PF3, PF4
[When used as trace data output pin
(xFRn<PxmFn>=1)] (note)
PA7 to PA0, PB7 to PB0, PE6 to PE0, PP6
to PP2, PP0
(When used as external bus pin
(PxFRn<PxmFn>=1). Only data bus pin and
input is enabled (PxIE <PxmIE>=1) (note)
other port pin
Note:x : port number / m : corresponding bit / n: function register number
Pin name
Output only
Input only
Input only
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
Page 50
"High" level output
<DRVE> = 0
×
×
×
×
×
×
ο
ο
ο
ο
Depends on (PxCR[m])
Depends on (PxCR[m])
Depends on (PxCR[m])
Depends on (PxCR[m])
Depends in (PxCR[m])
Depends on (PxIE[m])
Depends in (PxIE[m])
"High" level output
<DRVE> = 1
TMPM361F10FG
×
ο
ο
ο
ο