TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 296

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

10.3
Description of Registers
10.3.5
31-20
19-17
16-14
13-11
10-8
7-4
3-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
ifications of the memory to be used. Adjust base clock is SMCCLK : fsys/2.
rect_cmd register.
−
Set_t5[2:0]
Set_t4[2:0]
Set_t3[2:0]
Set_t2[2:0]
Set_t1[3:0]
Set_t0[3:0]
This register is provided to adjust the access cycle of static memory and should be set to satisfy the A.C. spec-
To validate SMC set cycles register setting, it is necessary to execute update register command on smc_di-
Bit Symbol
smc_set_cycles (SMC Set Cycles Register)
Note:It needs to keep below relation.
Undefined
Undefined
Undefined
Undefined
31
23
15
7
-
-
<Set_t3>,<Set_t1>
<Set_t2>,<Set_t0>
Set_t4
W
W
W
W
W
W
W
Type
Undefined
Undefined
Undefined
Undefined
30
22
14
6
-
-
Write as "0".
Set value of t
000 : Setting prohibition
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Set value of t
000 : Setting prohibition
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Page access is not supported in multiplex bus mode. t
Set value of t
000 : Setting prohibition
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
In multiplex mode, write pulse width (t
Set value of t
000 : Setting prohibition
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Set value of t
0000 : Setting prohibition
0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock
Set value of t
0000 : Setting prohibition
0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock
Set_t1
Undefined
Undefined
Undefined
Undefined
TR
PC
WP
CEOE
WC
RC
29
21
13
Multiplex bus mode :(t
Multiplex bus mode :(t
5
-
-
(note)
(note)
(note)
(note)
Page 272
Undefined
Undefined
Undefined
Undefined
Set_t3
28
20
12
4
-
-
WP
WP
CEOE
) increase for one more clock pulse against for value of <Set_t3>.
+ SMCCLK × 3 clock) ≤ t
Undefined
Undefined
Undefined
Undefined
+ SMCCLK × 1 clock) ≤ t
27
19
11
Function
3
-
PC
is effective only separate bus mode.
Undefined
Undefined
Undefined
Undefined
Set_t5
26
18
10
2
-
WC
RC
Set_t0
Undefined
Undefined
Undefined
Undefined
Set_t2
25
17
9
1
-
TMPM361F10FG
Undefined
Undefined
Undefined
Undefined
Set_t4
24
16
8
0
-