TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 453

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

INTSBIx
interrupt request
<PIN>
SCLx pin
SDAx pin
Figure 14-12 Terminating Data Transmission in the Master Receiver Mode
INTSBIx interrupt (after data transmission)
INTSBIx interrupt (first to (N-2)th data reception)
INTSBIx interrupt ((N-1)th data reception)
INTSBIx interrupt (Nth data reception)
INTSBIx interrupt (after completing data reception)
SBIxCR1
Reg.
End of interrupt
Reg.
End of interrupt
SBIxCR1
Reg.
End of interrupt
SBIxCR1
Reg.
End of interrupt
Processing to generate the stop condition.
End of interrupt
ated to terminate the data transfer.
In the interrupt processing for terminating the reception of 1-bit data, the stop condition is gener-
9
Example: When receiving N data word
Note:X; Don’t care
←
←
←
←
←
←
←
D7
7
X
SBIxDBR
7
SBIxDBR
7
X
SBIxDBR
7
0
SBIxDBR
1
Read receive data aftwer clear <ACK> to “0”
6
X
6
6
X
6
0
D6
5
X
5
5
X
5
1
2
4
X
4
4
0
4
0
D5
3
3
0
3
3
0
3
0
2
X
2
2
X
2
X
D4
4
1
X
1
1
X
1
X
Page 429
0
X
0
0
X
0
X
D3
5
Sets the number of bits of data to be received and
specify whether ACK is required.
Reads dummy data.
Reads the first to (N-2)th data words.
Disables generation of acknowledgement clock.
Reads the (N-1)th data word.
Disables generation of acknowledgement clock.
Reads the Nth data word.
Terminates the data transmission.
D2
6
D1
7
D0
8
Read receive data after
set <BC[2:0]> to “001”.
1
Master output
Slave output
Acknowlegment signal to
transmitter “High”
TMPM361F10FG