TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 535

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

17.4
17.4.1
WDT counter
INTWDT
WDT clear
WDTOUT
Operation when malfunction (runaway) is detected
ble interrupt (NMI). Thus CPU detects non-maskable interrupt and performs the countermeasure program.
rupts. In the case of INTWDT interrupt, CGNMIFLG<NMIFLG0> is set.
WDTOUT becomes "High" by the watchdog timer clearing that is writing clear code 0x4E to the WDCR reg-
ister.
In the Figure 17-2 shows the case that INTWDT interrupt generates (WDMOD<RESCR>="0").
When an overflow of the binary counter occurs, INTWDT interrupt generates. It is a factor of non-maska-
The factor of non-maskable interrupt is the plural. CGNMIFLG identifies the factor of non-maskable inter-
When INTWDT interrupt generates, simultaneously the watchdog timer out (WDTOUT) output "Low".
INTWDT interrupt generation
Figure 17-2 INTWDT interrupt generation
n
Overflow
Page 511
Write of a clear code
TMPM361F10FG
0