TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 269

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

9.4.2
31-2
1
0
DMACCxConfiguration<ITC>
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
DMACCxConfiguration<IE>
Bit
-
IntStatus1
IntStatus0
DMACIntStatus (DMAC Interrupt Status Register)
DMA terminal count
Bit Symbol
DMA transfer error
Undefined
Undefined
Undefined
Undefined
31
23
15
7
-
-
-
-
W
R
R
Type
Undefined
Undefined
Undefined
Undefined
30
22
14
Figure 9-2 Interrupt-related block diagram
6
Write as zero.
Status of DMAC channel 1 transfer end interrupt.
0 : Interrupt not requested
1 : Interrupt requested
Status of the DMAC interrupt generation after passing through the transfer end interrupt enable register
and error interrupt enable register. An interrupt is requested when there is a transfer error or when the coun-
ter completes counting.
Status of DMAC channel 0 interrupt generation.
0 : Interrupt not requested
1 : Interrupt requested
Status of the DMAC interrupt generation after passing through the transfer end interrupt enable register
and error interrupt enable register. An interrupt is requested when there is a transfer error or when the coun-
ter completes counting.
-
-
-
-
Undefined
Undefined
Undefined
Undefined
29
21
13
5
-
-
-
-
Page 245
Undefined
Undefined
Undefined
Undefined
28
20
12
4
-
-
-
-
DMACIntTCStatus (Masked terminal count interrupt)
DMACIntErrorStatus (Masked transfer error interrupt)
DMACIntStatus
DMACRawIntTCStatus (Terminal count interrupt prior to masking)
DMACRawIntErrorStatus (Transfer error interrupt prior to masking)
Undefined
Undefined
Undefined
Undefined
Description
27
19
11
3
-
-
-
-
Undefined
Undefined
Undefined
Undefined
26
18
10
2
-
-
-
-
Undefined
Undefined
Undefined
IntStatus1
25
17
9
1
0
-
-
-
TMPM361F10FG
Undefined
Undefined
Undefined
IntStatus0
24
16
8
0
0
-
-
-