TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 447

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

14.5.11
14.5.12
14.5.13
14.5.14
Figure 14-8 Example of Master B Lost Arbitration (D7A = D7B, D6A = D6B)
SBIxSR<AAS> is set to "1" on receiving the general-call address or the slave address that matches the value
specified at SBIxI2CAR.
to "0" when data is written to or read from SBIxDBR.
dress; i.e., the eight bits following the start condition are all zeros.
rupt request causes ACK signal to be read.
start condition.
When the SBI operates as a slave device in the address recognition mode (SBIxI2CAR<ALS>="0"),
When <ALS> is "1", <AAS> is set to "1" when the first data word has been received. <AAS> is cleared
When the SBI operates as a slave device, SBIxSR<AD0> is set to "1" when it receives the general-call ad-
<AD0> is cleared to "0" when the start or stop condition is detected on the bus.
SBIxSR<LRB> is set to the SDA line value that was read at the rising of the SCL line.
In the acknowledgment mode, reading SBIxSR<LRB> immediately after generation of the INTSBIx inter-
Reading or writing SBIxDBR initiates reading received data or writing transmitted data.
When the SBI is acting as a master, setting a slave address and a direction bit to this register generates the
Access to SBIxDBR or
SBIxCR2
MasterA
MasterB
Slave Address Match Detection Monitor
General-call Detection Monitor
Last Received Bit Monitor
Data Buffer Register (SBIxDBR)
<AL>
<MST>
<TRX>
Internal SCL
Internal SDA
Internal SCL
InternalSDA
output
output
output
output
D7A D6A
D7B D6B
1
1
2
2
D5A D4A
3
3
Internal SDA output is fixed to "High"level .
due to Arbitration Lost of Master B.
4
4
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D3A D2A D1A
5
Clock output dstops here
6
7
D0A
8
9
D7A'
1
D6A'
2
TMPM361F10FG
D5A' D4A'
3
4