TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 14

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

9. DMA Controller(DMAC)
10. Static Memory Controller
vi
9.1 Function Overview................................................................................................................241
9.2 DMA transfer type.................................................................................................................242
9.3 Block diagram.......................................................................................................................243
9.4 Description of Registers........................................................................................................244
9.5 Special Functions...................................................................................................................264
10.1 Function Overview..............................................................................................................267
10.2 Block diagram.....................................................................................................................267
10.3 Description of Registers......................................................................................................268
10.4 External Bus Cycle .............................................................................................................282
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10
8.4.11
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.4.11
9.4.12
9.4.13
9.4.14
9.4.15
9.4.16
9.4.17
9.5.1
9.5.2
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
10.3.10
10.3.11
10.3.12
10.3.13
10.3.14
10.4.1
10.4.1.1
Port B Setting..................................................................................................................................................................231
Port E Setting..................................................................................................................................................................232
Port F Setting...................................................................................................................................................................233
Port G Setting..................................................................................................................................................................234
Port I Setting....................................................................................................................................................................235
Port J Setting...................................................................................................................................................................236
Port L Setting..................................................................................................................................................................237
Port M Setting.................................................................................................................................................................238
DMAC register list..........................................................................................................................................................244
DMACIntStatus (DMAC Interrupt Status Register)......................................................................................................245
DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register)......................................................................246
DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register).........................................................................247
DMACIntErrorStatus (DMAC Interrupt Error Status Register)....................................................................................248
DMACIntErrClr (DMAC Interrupt Error Clear Register).............................................................................................249
DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register)......................................................250
DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register)....................................................................251
DMACEnbldChns (DMAC Enabled Channel Register)................................................................................................252
Scatter/gather function.....................................................................................................................................................264
Linked list operation........................................................................................................................................................265
Port N setting.................................................................................................................................................................239
Port P Setting.................................................................................................................................................................240
DMACSoftBReq (DMAC Software Burst Request Register).....................................................................................253
DMACSoftSReq (DMAC Software Single Request Register)....................................................................................255
DMACConfiguration (DMAC Configuration Register)...............................................................................................256
DMACCxSrcAddr (DMAC Channelx Source Address Register)...............................................................................257
DMACCxDestAddr (DMAC Channelx Destination Address Register)......................................................................258
DMACCxLLI (DMAC Channelx Linked List Item Register).....................................................................................259
DMACCxControl (DMAC Channelx Control Register)..............................................................................................260
DMACCxConfiguration (DMAC Channelx Configuration Register)..........................................................................262
SFR List.........................................................................................................................................................................268
SMCMDMODE (Mode Register).................................................................................................................................269
smc_memif_cfg (SMC Memory Interface Configuration Register)............................................................................270
smc_direct_cmd (SMC Direct Command Register).....................................................................................................271
smc_set_cycles (SMC Set Cycles Register).................................................................................................................272
smc_set_opmode (SMC Set Opmode Register)...........................................................................................................273
smc_sram_cycles0_0 (SMC SRAM Cycles Registers 0 <0>).....................................................................................274
smc_sram_cycles0_1 (SMC SRAM Cycles Registers 0 <1>).....................................................................................275
smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 <2>).....................................................................................276
Multiplex mode..............................................................................................................................................................282
smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 <3>)...................................................................................277
smc_opmode0_0 (SMC Opmode Registers 0<0>).....................................................................................................278
smc_opmode0_1 (SMC Opmode Registers 0<1>).....................................................................................................279
smc_opmode0_2 (SMC Opmode Registers 0<2>).....................................................................................................280
smc_opmode0_3 (SMC Opmode Registers 0<3>).....................................................................................................281
tRC / tCEOE setting example