TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 17

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13. Synchronous Serial Port (SSP)
14. Serial Bus Interface (I2C/SIO)
13.1 Overview..............................................................................................................................383
13.2 Block Diagram.....................................................................................................................384
13.3 Register................................................................................................................................385
13.4 Overview of SSP.................................................................................................................395
13.5 SSP operation......................................................................................................................399
13.6 Frame Format......................................................................................................................400
14.1 Configuration.......................................................................................................................408
14.2 Register................................................................................................................................409
14.3 I2C Bus Mode Data Format................................................................................................410
14.4 Control Registers in the I2C Bus Mode..............................................................................411
14.5 Control in the I2C Bus Mode..............................................................................................418
12.16.4
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.3.11
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.5.1
13.5.2
13.5.3
13.6.1
13.6.2
13.6.3
14.2.1
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
12.16.4.1
12.16.4.2
14.5.1.1
14.5.1.2
Register List...................................................................................................................................................................385
SSPCR0(Control register 0)..........................................................................................................................................386
SSPCR1(Control register1)...........................................................................................................................................387
SSPDR(Data register)....................................................................................................................................................388
SSPSR(Status register)..................................................................................................................................................389
SSPCPSR (Clock prescale register)..............................................................................................................................390
SSPIMSC (Interrupt enable/disable register)................................................................................................................391
SSPRIS (Pre-enable interrupt status register)...............................................................................................................392
SSPMIS (Post-enable interrupt status register)............................................................................................................393
Clock prescaler..............................................................................................................................................................395
Transmit FIFO...............................................................................................................................................................395
Receive FIFO.................................................................................................................................................................395
Interrupt generation logic..............................................................................................................................................396
DMA interface...............................................................................................................................................................398
Initial setting for SSP....................................................................................................................................................399
Enabling SSP.................................................................................................................................................................399
Clock ratios....................................................................................................................................................................399
SSI frame format...........................................................................................................................................................401
SPI frame format...........................................................................................................................................................402
Microwire frame format................................................................................................................................................404
Registers for each channel............................................................................................................................................409
SBIxCR0(Control register 0)........................................................................................................................................411
SBIxCR1(Control register 1)........................................................................................................................................412
SBIxCR2(Control register 2)........................................................................................................................................414
SBIxSR (Status Register)..............................................................................................................................................415
SBIxBR0(Serial bus interface baud rate register 0).....................................................................................................416
SBIxDBR (Serial bus interface data buffer register)....................................................................................................416
SBIxI2CAR (I2Cbus address register)..........................................................................................................................417
Serial Clock...................................................................................................................................................................418
Setting the Acknowledgement Mode............................................................................................................................419
Setting the Number of Bits per Transfer......................................................................................................................419
Slave Addressing and Address Recognition Mode......................................................................................................419
Operating mode.............................................................................................................................................................419
Configuring the SBI as a Transmitter or a Receiver....................................................................................................420
Configuring the SBI as a Master or a Slave.................................................................................................................420
Mode 3 (9-bit UART Mode).......................................................................................................................................380
SSPICR (Interrupt clear register)................................................................................................................................394
SSPDMACR (DMA control register).........................................................................................................................394
Clock source
Clock Synchronization
Wake-up Function
Protocol
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