TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 390

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.14
Interrupt / Error Generation Timing
12.14.2
TXD
12.14.2.1
12.14.2.2
Figure 12-11 shows the data flow of transmit operation and the route of read.
which are given as follows.
SCxTFC<TFIS> setting are established.
Table 12-14 Transmit Interrupt conditions in use of FIFO
If the transmit buffer is empty,
TX interrupt
SCxTFC<TFIS>
TX interrupts are generated at the time depends on the transfer mode and the buffer configurations,
Buffer Configuration
In use of FIFO, transmit interrupt is generated on the condition that the following either operation and
Interrupt conditions are decided by the SCxTFC<TFIS> settings as described in Table 12-14.
Note:If double buffer is enabled, a interrupt is also generated when the data is moved from the buf-
If the shift register is empty,
Double Buffer
Single Buffer
Single Buffer / Double Buffer
FIFO
Figure 12-11 Transmit Buffer / FIFO Configuration Diagram
・ Transmission completion of all bits of one frame.
・ Writing FIFO
"0"
"1"
fer to the shift register by writing to the buffer.
the data is moved.
the data is moved.
"The fill level of FIFO" is smaller than or equal to "the fill level of FIFO interruption generation."
TX FIFO First stage
Just before the stop bit is sent
When a data is moved from the transmit buffet to the transmit shift register.
Transmit shift register
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
Transmit buffer
UART modes
Second stage
Third stage
Fourth stage
Page 366
Interrupt condition
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
(1)Writing in the single buffer configuration :
(2)Writing in the double buffer configuration :
(3)Writing in use the FIFO :
An interrupt is generated after transmitting all bits.
An interrupt is generated when the data is moved to
the transmit shift register.
An interrupt is generated
When the data is moved to the transmit buffer
or when wrting to the FIFO.
I/O interface modes
TMPM361F10FG