TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 499

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

(2)
(3)
(4)
sion interrupt or a minimum cycle error interrupt.
terrupt sets the CECRSTAT <CECRIMIN> bit.
2.0 ms from the starting point (the falling edge) of the ACK bit.
not. If it is "Low", an ACK collision interrupt is generated. If it is "High", and "Low" is detected dur-
ing the detection period, the minimum cycle error interrupt is generated. The minimum cycle error cau-
ses CEC to output "Low" for approx. 3.63ms.
reading the data stored in the receive buffer.
interrupt is generated.
Note 2: If the initiator sends a new message beginning with the start bit without having sent the last block with
At an ACK response, detecting "Low" after the specified period to output generates an ACK colli-
The ACK collision interrupt sets the CECRSTAT <CECRIACK> bit. The minimum cycle error in-
The following describes the period and method of detection.
Detection starts approx. 0.3 ms after the end of the period of outputting "Low" and ends approx
At 0.3 ms from the end of the period of outputting "Low", CEC checks if the CEC line is "0" or
A receive buffer overrun interrupt is generated when the next data reception is completed before
The interrupt sets the CECRSTAT <CECRIOR> bit.
A waveform error occurs when waveform error detection is enabled in CECRCR3.
Detecting a waveform, which does not identical to the defined, results in the waveform error. The
The interrupt sets the CECRSTAT <CECRIWAV> bit.
Receive Buffer Overrun
Waveform Error
Beginning of ACK bit
ACK Collision
EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt is generated. For de-
taled information, refer to "15.1.3 Precautions".
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2.0 ms
End of
“Low” output
0.3 ms
Detection
period
TMPM361F10FG