TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 53

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

5.2
5.3
5.2.1
tion registers.
ister and the FCSECBIT register are initialized by a only cold reset.
Warm reset
After reset
A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal func-
The processor core's system debug components (FPB, DWT, ITM) register, the clock generator's CGRSTFLG reg-
After reset, the PLL multiplication circuit is inactive and must be enabled in the CGPLLSEL register if needed.
When the reset exception handling is completed, the program branches to the reset interrupt service routine.
Note:The reset operation may alter the internal RAM state.
frequency oscillator is providing stable oscillation.
clocks.
400μs.
Reset period
As a precondition, ensure that the power supply voltage is within the operating range and the internal high-
To reset the TMPM361F10FG, assert the RESET signal (active low) for a minimum duration of 12 system
After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further
Page 29
TMPM361F10FG