TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 643

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

22.2.10.6
nications between the controller and the target board, the controller must firstly send a value of 0x86 at a
desired baud rate to the target board. To use I/O Interface mode, the controller must send a value of 0x30
at 1/16 of the desired baud rate. Figure 22-4 shows the waveforms for the first byte in each mode.
SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Figure 22-5 shows a flowchart
describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot
program captures timer counts when each time the logic transition occurs in the first serial byte. Consequent-
ly, the calculated tAB, tAC and tAD intervals tend to have slight errors. If the transfer goes at a high
baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive
pin. In particular, I/O Interface mode may have this problem since its baud rate is generally much higher
than that for UART mode. To avoid such a situation, the controller should send the first serial byte at
1/16 of the desired baud rate.
face modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is de-
termined as UART mode. If the length of tAB is greater than the length of tCD, the serial operation
mode is determined as I/O Interface mode. Note that if the baud rate is too high or the timer operating fre-
quency is too low, each timer value becomes small. It causes an unintentional behavior of the controller.
To prevent this problem, reset UART mode within the programming routine.
mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should al-
low for a time-out period within which it expects to receive an echo-back (0x86) from the target board.
The controller should give up the communication if it fails to get that echo-back within the allowed time.
When I/O Interface mode is utilized, once the first serial byte has been transmitted, the controller should
send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowl-
edge response is not 0x30, the controller should give up further communications.
is greater than tCD as shown above. 0x91, 0xA1 or 0xB1 can be sent as the first byte code to determine
the falling edges of Point A and Point C and the rising edges of Point B and Point D. If tAB is greater
than tCD and SIO is selected by the resolution of the operation mode determination, the second byte
code is 0x30 even though the transmitted code on the first byte is not 0x30 (The first byte code to deter-
mine I/O interface mode is described as 0x30).
I/O Interface
UART (0x86)
The first byte from the controller determines the serial operation mode. To use UART mode for commu-
After RESET is released, the boot program monitors the first serial byte from the controller, with the
The flowchart in Figure 22-5 shows how the boot program distinguishes between UART and I/O Inter-
For example, the serial operation mode may be determined to be I/O Interface mode when the intended
When the intended mode is I/O interface mode, the first byte does not have to be 0x30 as long as tAB
(0x30)
Determination of a Serial Operation Mode
Point A
Point A
Figure 22-4 Serial Operation Mode Byte
Start
bit 0
tAB
bit 0
bit 1
Point B
tAB
bit 1
bit 2
Page 619
bit 2
bit 3
Point C
Point B
bit 3
bit 4
bit 5
bit 4
Point C
tCD
bit 6
bit 5
tCD
bit 7
bit 6
Point D
Point D
bit 7
TMPM361F10FG
Stop