TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 16

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

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12.5 Operation in Each Mode.....................................................................................................339
12.6 Data Format.........................................................................................................................340
12.7 Clock Control......................................................................................................................342
12.8 Transmit / Receive Buffer and FIFO..................................................................................352
12.9 Status Flag...........................................................................................................................353
12.10 Error Flag...........................................................................................................................353
12.11 Receive..............................................................................................................................355
12.12 Transmission......................................................................................................................360
12.13 Handshake Function..........................................................................................................364
12.14 Interrupt / Error Generation Timing.................................................................................365
12.15 Software Reset...................................................................................................................367
12.16 Operation in Each Mode...................................................................................................368
12.4.10
12.4.11
12.4.12
12.4.13
12.6.1
12.6.2
12.6.3
12.7.1
12.7.2
12.8.1
12.8.2
12.8.3
12.10.1
12.10.2
12.10.3
12.11.1
12.11.2
12.11.3
12.12.1
12.12.2
12.12.3
12.14.1
12.14.2
12.14.3
12.16.1
12.16.2
12.16.3
12.6.2.1
12.6.2.2
12.7.2.1
12.7.2.2
12.11.2.1
12.11.2.2
12.11.3.1
12.11.3.2
12.11.3.3
12.11.3.4
12.11.3.5
12.11.3.6
12.12.2.1
12.12.2.2
12.12.3.1
12.12.3.2
12.12.3.3
12.12.3.4
12.14.1.1
12.14.1.2
12.14.2.1
12.14.2.2
12.14.3.1
12.14.3.2
12.16.1.1
12.16.1.2
12.16.1.3
Data Format List............................................................................................................................................................340
Parity Control................................................................................................................................................................341
STOP Bit Length...........................................................................................................................................................341
Prescaler.........................................................................................................................................................................342
Serial Clock Generation Circuit....................................................................................................................................348
Configuration.................................................................................................................................................................352
Transmit / Receive Buffer.............................................................................................................................................352
FIFO...............................................................................................................................................................................352
SCxRFC (RX FIFO Configuration Register).............................................................................................................335
SCxTFC (TX FIFO Configuration Register) (Note2)................................................................................................336
SCxRST (RX FIFO Status Register)..........................................................................................................................337
SCxTST (TX FIFO Status Register)...........................................................................................................................338
OERR Flag..................................................................................................................................................................353
PERR Flag...................................................................................................................................................................354
FERR Flag...................................................................................................................................................................354
Receive Counter..........................................................................................................................................................355
Receive Control Unit...................................................................................................................................................355
Receive Operation.......................................................................................................................................................355
Transmission Counter..................................................................................................................................................360
Transmission Control..................................................................................................................................................360
Transmit Operation......................................................................................................................................................361
RX Interrupt.................................................................................................................................................................365
TX interrupt.................................................................................................................................................................366
Error Generation..........................................................................................................................................................367
Mode 0 (I/O Interface Mode)......................................................................................................................................368
Mode 1 (7-bit UART Mode).......................................................................................................................................379
Mode 2 (8-bit UART Mode).......................................................................................................................................379
Transmission
Receiving Data
Baud Rate Generator
Clock Selection Circuit
I/O interface mode
UART Mode
Receive Buffer
Receive FIFO Operation
I/O interface mode with SCLK output
Read Received Data
Wake-up Function
Overrun Error
I/O interface Mode
UART Mode
Operation of Transmission Buffer
Transmit FIFO Operation
I/O interface Mode/Transmission by SCLK Output
Underrun Error
Single Buffer / Double Buffer
FIFO
Single Buffer / Double Buffer
FIFO
UART Mode
I/O Interface Mode
Transmitting Data
Receive
Transmit and Receive (Full duplex)