TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 284

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

9.4
Description of Registers
9.4.16
31
30-28
27
26
25-24
23-21
20-18
17-15
14-12
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
I
-
DI
SI
-
Dwidth[2:0]
Swidth[2:0]
DBSize[2:0]
SBSize[2:0]
Bit Symbol
DMACCxControl (DMAC Channelx Control Register)
DBSize
31
23
15
0
0
0
7
0
I
R/W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
Type
Undefined
Dwidth
30
22
14
0
0
6
0
-
Bit for enabling a transfer interrupt.
(It is enabled in scatter/gather function.)
0 : Disable
1 : Enable
The transfer end interrupt is generated by setting <I>="1" and DMACCxConfiguration<ITC>="1". While the
scatter/gather function is used in the setting of the last DMAC transfer, if this bit is set to 1, the transfer
end interrupt is generated only at the last transfer. To generate interrupt during normal transfer, set this bit
to "1" and change to enable mode.
Write as zero.
Increment the transfer destination address
0 : Do not increment
1 : Increment
Increment the transfer source address
0 : Do not increment
1 : Increment
Write as zero.
Transfer destination bit width.
000 : Byte (8 bits)
001 : Half-word (16 bits)
010 : Word (32 bits)
other: Reserved
Transfer source bit width
000: Byte (8 bits)
001: Half-word (16 bits)
010 : Word (32 bits)
other: Reserved
Transfer destination burst size: (Note 1)
Transfer source burst size: (Note 1)
000: 1 beat
001: 4 beats
010: 8 beats
011: 16 beats
000: 1 beat
001: 4 beats
010: 8 beats
011: 16 beats
Undefined
SBSize
29
21
13
0
0
5
0
-
Page 260
Undefined
28
20
12
0
0
4
0
-
TransferSize
100: 32 beats
101: 64 beats
110: 128 beats
111: 256 beats
100: 32 beats
101: 64 beats
110: 128 beats
111: 256 beats
Swidth
Description
27
19
11
DI
0
0
0
3
0
26
18
10
SI
0
0
0
2
0
TransferSize
Undefined
25
17
0
9
0
1
0
-
TMPM361F10FG
DBSize
Undefined
24
16
0
8
0
0
0
-