TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 658

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

22.3
On-board Programming of Flash Memory (Rewrite/Erase)
Normal
commands
ID-READ
Block erase
Auto page
program-
ming
Protection
bit pro-
gramming
Protection
bit erase
22.3.2
Address
first bus cycle. "0" is recommended" in the Table 22-16 Address Bit Configuration for Bus Write Cycles can
be changed as necessary.
Table 22-16 is used in conjunction with "Table 22-15 Flash Memory Access from the Internal CPU".
Address setting can be performed according to the normal bus write cycle address configuration from the
As block address, specify any address in the block to be erased.
Address bit configuration for bus write cycles
Flash area
Flash area
Flash area
Flash area
Note:As for the addresses from the first to the fifth bus cycles, specify the upper addresses of the
[31:20]
Addr
blocks to be erased.
Block selection (Table 22-16)
Table 22-16 Block Address Table
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
Block
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
Fixed
Fixed
Addr
8
9
7
6
5
4
3
2
1
0
[19]
"0".
"0".
to
to
"0" is recommended.
"0" is recommended.
BA: Block address (Set the sixth bus write cycle address for block erase operation)
0x000C_0000 to 0x000D_FFFF
0x000A_0000 to 0x000B_FFFF
0x000E_0000 to 0x000F_FFFF
0x0000_8000 to 0x0000_FFFF
0x0001_0000 to 0x0001_FFFF
0x0002_0000 to 0x0003_FFFF
0x0004_0000 to 0x0005_FFFF
0x0006_0000 to 0x0007_FFFF
0x0008_0000 to 0x0009_FFFF
0x0000_0000 to 0x0000_7FFF
(Table 22-17)
(Table 22-18)
Protection bit
Protection bit
Addr
[18]
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
selection
selection
(User boot mode)
Addr
[17]
Address
Addr
Page selection
[16]
Normal bus write cycle address configuration
Addr
[15]
ID address
Page 634
Fixed to "0".
Addr
0x3F8A_0000 to 0x3F8B_FFFF
0x3F8C_0000 to 0x3F8D_FFFF
0x3F8E_0000 to 0x3F8F_FFFF
[14]
0x3F80_0000 to 0x3F80_7FFF
0x3F80_8000 to 0x3F80_FFFF
0x3F81_0000 to 0x3F81_FFFF
0x3F82_0000 to 0x3F83_FFFF
0x3F84_0000 to 0x3F85_FFFF
0x3F86_0000 to 0x3F87_FFFF
0x3F88_0000 to 0x3F89_FFFF
Fixed to "0".
(Single boot mode)
Address
Addr[1:0]="0" (fixed), Others:0 (recommended)
[13:11]
Addr
Command
Addr[1:0]="0" (fixed), Others:0 (recommended)
Protect bit se-
(Table 22-17)
Addr
[10]
lection
(Kbyte)
Size
128
128
128
128
128
128
128
32
32
64
Addr
[9]
Others:0 (recommended)
Addr[1:0]="0" (fixed)
Addr
[8]
Others:0 (recommended)
Others:0 (recommended)
TMPM361F10FG
Addr[1:0]="0" (fixed)
Addr[1:0]="0" (fixed)
Addr[1:0]="0" (fixed)
(recommended)
Others:0
Addr
[7:0]