TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 551

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.6
KEY input
The timing of interrupt
Result of an internal sampling
KWUP input Detection Timing
1. PJPUP<PJnUP>="1", KWUPCRn<DPEn>="0" with always pull-up
2. PJPUP<PJnUP>="1", KWUPCRn<DPEn>="1" with dynamic pull-up
edges by setting KWUPCRn<KEYn>. The active state of key inputs are continuously detected.
before fs at the end of the T1 period. Therefore, a key input not shorter than the T2 period is nee-
ded.There is a delay up to the T2 period before key input detection. The figure below shows an example
of defining the active state to the falling edge.
The active state of each key input can be defined to the high or low level or to the rising or falling
Detection of the active state of each key input (interrupt detection) is carried out at the edge one-clock
Pull-up (period of T1)
High or Hi-Z
Cycle (period of T2)
Need more than T2 period (Low period)
Page 527
KEY input Detection
High or Hi-Z or Low
TMPM361F10FG