TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 18

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15. Consumer Electronics Control (CEC)
x
14.6 Data Transfer Procedure in the I2C Bus ModeI2C............................................................425
14.7 Control register of SIO mode..............................................................................................434
14.8 Control in SIO mode...........................................................................................................440
15.1 Outline.................................................................................................................................447
15.2 Block Diagram.....................................................................................................................448
15.3 Registers..............................................................................................................................449
15.4 Operations............................................................................................................................468
14.5.8
14.5.9
14.5.10
14.5.11
14.5.12
14.5.13
14.5.14
14.5.15
14.5.16
14.6.1
14.6.2
14.6.3
14.6.4
14.6.5
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
14.8.1
14.8.2
15.1.1
15.1.2
15.1.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
15.3.7
15.3.8
15.3.9
15.3.10
15.3.11
15.3.12
15.3.13
15.3.14
15.3.15
15.4.1
15.4.2
14.6.2.1
14.6.2.2
14.6.3.1
14.6.3.2
14.8.1.1
14.8.1.2
14.8.2.1
14.8.2.2
14.8.2.3
14.8.2.4
15.4.2.1
15.4.2.2
Generating Start and Stop Conditions..........................................................................................................................420
Interrupt Service Request and Release.........................................................................................................................421
Device Initialization......................................................................................................................................................425
Generating the Start Condition and a Slave Address...................................................................................................425
Transferring a Data Word.............................................................................................................................................427
Generating the Stop Condition......................................................................................................................................432
Restart Procedure...........................................................................................................................................................432
SBIxCR0(control register 0).........................................................................................................................................434
SBIxCR1(Control register 1)........................................................................................................................................435
SBIxDBR (Data buffer register)...................................................................................................................................436
SBIxCR2(Control register 2)........................................................................................................................................437
SBIxSR (Status Register)..............................................................................................................................................438
SBIxBR0 (Baud rate register 0)....................................................................................................................................439
Serial Clock...................................................................................................................................................................440
Transfer Modes..............................................................................................................................................................442
Reception.......................................................................................................................................................................447
Transmission..................................................................................................................................................................447
Precautions.....................................................................................................................................................................447
Register List...................................................................................................................................................................449
CECEN (CEC Enable Register)....................................................................................................................................450
CECADD (Logical Address Register ).........................................................................................................................451
CECRESET (Software Reset Register)........................................................................................................................452
CECREN (Receive Enable Register)............................................................................................................................453
CECRBUF (Receive Buffer Register)..........................................................................................................................454
CECRCR1 (Receive Control Register 1)......................................................................................................................455
CECRCR2 (Receive Control Register 2)......................................................................................................................457
CECRCR3 (Receive Control Register 3 )....................................................................................................................459
Sampling clock..............................................................................................................................................................468
Reception.......................................................................................................................................................................468
Arbitration Lost Detection Monitor............................................................................................................................421
Slave Address Match Detection Monitor....................................................................................................................423
General-call Detection Monitor...................................................................................................................................423
Last Received Bit Monitor..........................................................................................................................................423
Data Buffer Register (SBIxDBR)...............................................................................................................................423
Baud Rate Register (SBIxBR0)..................................................................................................................................424
Software Reset.............................................................................................................................................................424
CECTEN (Transmit Enable Register).........................................................................................................................461
CECTBUF (Transmit Buffer Register).......................................................................................................................462
CECTCR (Transmit Control Register).......................................................................................................................463
CECRSTAT (Receive Interrupt Status Register).......................................................................................................465
CECTSTAT (Transmit Interrupt Status Register)......................................................................................................466
CECFSSEL(CEC Sampling Clock Select Register)...................................................................................................467
Master mode
Slave mode
Master mode (<MST> = "1")
Slave mode (<MST> = "0")
Clock source
Shift Edge
8-bit transmit mode
8-bit receive mode
8-bit transmit/receive mode
Data retention time of the last bit at the end of transmission
Basic Operation
Preconfiguration