TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 378

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TMPM361F10FG

Manufacturer Part Number
TMPM361F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM361F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Contact Us
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14Ã?14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
3
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM361F10FG
Manufacturer:
Toshiba
Quantity:
10 000
12.10
Error Flag
12.10.2
12.10.3
from the parity received.
abled.
the transmit shift register with no data in the transmit buffer.
stops.
around the center. Regardless of the stop bit length settings in the SCxMOD2<SBLEN>register, the stop bit sta-
tus is determined by only 1.
This flag indicates a parity error in the UART mode and an under-run error in the I/O interface mode.
In the UART mode, <PERR> is set to "1" when the parity generated from the received data is different
In the I/O interface mode, <PERR> is set to "1" under the following conditions when a double buffer is en-
In the SCLK input mode, <PERR> is set to "1" when the SCLK is input after completing data output of
In the SCLK output mode, <PERR> is set to "1" after completing output of all data and the SCLK output
A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at
This bit is fixed to "0" in the I/O interface mode.
Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and
Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and
PERR Flag
FERR Flag
clear the overrun flag.
clear the underrun flag.
Page 354
TMPM361F10FG

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