TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 96

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

7.5
Interrupts
standby mode
Not clearing
7.5.2
7.5.2.1
(clearing standby mode)
CPU handles interrupt.
CPU detects interrupt.
CG detects interrupt
Setting for detection
Interrupt generation
setting for sending
interrupt signal
Interrupt Handling
Processing
The following shows how an interrupt is handled.
Flowchart
The following shows how an exception/interrupt is handled. In the following descriptions,
indicates hardware handling.
standby mode
Clearing
Set the relevant NVIC registers for detecting interrupts.
Set the clock generator as well if each interrupt source is used to clear a stand-
by mode.
ο Common setting
NVIC registers
ο setting to clear standby mode
Clock generator
Execute an appropriate setting to send the interrupt signal depending on the in-
terrupt type.
ο Setting for interrupt from external pin
Port
ο Setting for interrupt from peripheral function
Peripheral function (See the chapter of each peripheral function for details.)
An interrupt request is generated.
Interrupt lines used for clearing a standby mode are connected to the CPU via
the clock generator.
The CPU detects the interrupt.
If multiple interrupt requests occur simultaneously, the interrupt request with
the highest priority is detected according to the priority order.
The CPU handles the interrupt.
The CPU pushes register contents to the stack before entering the ISR.
Page 72
indicates software handling.
Details
TMPM361F10FG
"7.5.2.5 CPU process-
"7.5.2.3 Detection by
"7.5.2.4 Detection by
"7.5.2.2 Preparation"
Clock Generator"
CPU"
See
ing"