TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 500

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15.4
Operations
15.4.2.6
ing data reception, receiving operation stops and the received data is discarded.
(5)
Writing "0" to the CECREN <CECREN> bit disables data reception. If the data reception is disabled dur-
Note:If the reception is disabled while "Low" is sent as a signal of minimum cycle error, the "Low" output
Stopping Reception
ded without generating an interrupt when an erro is detected. This can be set in the CECRCR1 <CE-
CRIHLD> bit. To enable the setting, a timeout setting with the CECRCR1 <CECTOUT> bit is re-
quired.
ing the ACK bit is completed, CEC generates an interrupt after a reversed ACK response is execu-
ted. "1" is set to the bits of the CECRSTAT register: the <CECRIEND> bit that indicates the recep-
tion completion, and the bits corresponding to the detected errors.
terrupt is generated after the timeout. "1" is set to the bits of the CECRSTAT register corresponding
to the detected error.
bus to be free in transmission.
out occurs. Thus, an interrupt is generated in each reception of a byte of data if multiple bytes are re-
ceived while interrupts are suspended. "1" is set to the bits of the CECRSTAT register: the <CE-
CRIEND> bit that indicates the reception completion, and the bits corresponding to the detected er-
rors. The flags of the suspended interrupts and the reception completion are set to the bits of the CECR-
STAT register.
Note 1: A minimum cycle error interrupt is generated upon detecting a minimum cycle error in the next
Note 2: If an interrupt other than a minimum cycle error interrupt is generated while interrupts are suspen-
is stopped as well.
You can specify if a maximum cycle error, a buffer overrun and a waveform error to be suspen-
Under suspend-enable condition, if CEC keeps receiving the next bit and the entire reception includ-
If the reception of the next bit is interrupted, CEC starts to measure the timeout period, and an in-
The timeout is measured from the end of the last bit received as is the case with wait time of a
The information that the interrupts are suspended is held until the EOM bit is received or the time-
Suspending Receive Error Interrupt
received bit while interrupts are suspended. "Low" is output to CEC for approx. 3.63 ms. The
flags of the suspended interrupts and the minimum cycle error are set to the bits of the CECR-
STAT register.
ded, CEC continues reception until the ACK response or the timeout. All the flags of the detec-
ted interrupts are set to the bits of the CECRSTAT register.
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TMPM361F10FG