TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 95

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

Table 7-3 List of Interrupt Sources
7.5.1.6
No.
89
90
91
92
93
94
95
96
97
98
99
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INTDMACERR
INTDMACTC0
ognizes interrupt signals in "High" level as interrupt. Interrupt signals directly sent from peripheral func-
tions to the CPU are configured to output "High" to indicate an interrupt request.
rupt requests from peripheral functions are set as rising-edge or falling-edge triggered. Interrupt requests
from interrupt pins can be set as level-sensitive ("High" or "Low") or edge-triggered (rising or falling).
is also required. Enable the CGIMCGx<INTxEN> bit and specify the active level in the
CGIMCGx<EMCGx> bits. You must set the active level for interrupt requests from each peripheral func-
tion as shown in Table 7-3
The active level indicates which change in signal of an interrupt source triggers an interrupt. The CPU rec-
Active level is set to the clock generator for interrupts which can be a trigger to release standby. Inter-
If an interrupt source is used for clearing a standby mode, setting the relevant clock generator register
An interrupt request detected by the clock generator is notified to the CPU with a signal in "High" level.
Active level
Note:For the CEC reception / transmission, remote control signal reception and real time clock in-
terrupts, set the <INTxEN> bit to "1" and specify the active level, even when they are not
used for clearing a standby mode.
-
-
-
-
-
-
-
-
-
DMA transmission error
DMA transmission completion
Interrupt Source
Page 71
(Clearing standby)
active level
CG interrupt mode
control register
TMPM361F10FG