TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 483

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TMPM361F10FG

Manufacturer Part Number
TMPM361F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM361F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Contact Us
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14Ã?14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
3
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM361F10FG
Manufacturer:
Toshiba
Quantity:
10 000
15.3.9
31-23
22-20
19
18-16
15
14-12
11
10-8
7-2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
CECWAV3[2:0]
CECWAV2[2:0]
CECWAV1[2:0]
CECWAV0[2:0]
CECRSTAEN
CECWAVEN
CECRCR3 (Receive Control Register 3 )
Bit Symbol
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
Type
30
22
14
0
0
0
6
0
-
-
Read as 0.
The latest rising timing of logical "0" determined as proper waveform.
000: 56/fs (approx. 1.709 ms)
001: 56/fs + 1/fs
001: 56/fs + 2/fs
011: 56/fs + 3/fs
Read as 0.
The fastest rising timing of logical "0" deterrmined as proper.
000: 43/fs (approx.1.312 ms)
001: 43/fs − 1/fs
010: 43/fs − 2/fs
011: 43/fs − 3/fs
Read as 0.
The latest rising timing of logical "1" determined as proper waveform.
000: 26/fs (approx. 0.793 ms)
001: 26/fs + 1/fs
001: 26/fs + 2/fs
011: 26/fs + 3/fs
Read as 0
The fastest rising timing of logical "1" determined as proper.
000: 13/fs (approx. 0.396 ms)
001: 13/fs − 1/fs
010: 13/fs − 2/fs
011: 13/fs − 3/fs
Read as 0.
Start bit detection
1: Enable
0: Disable
Detects a reception of start bit and generates interrupt.
Waveform error detection
1: Enable
0: Disable
Detects a received waveform does not identical to the one defined and generates waveform error interrupt.
If enabled, an error is detected according to the setting of <CECWAV0> <CECWAV1> <CECWAV2>
<CEC WAV3>.
CECWAV3
CECWAV1
29
21
13
0
0
0
5
0
-
-
Page 459
28
20
12
0
0
0
4
0
-
-
27
19
11
0
0
0
3
0
-
-
-
-
Function
100: 56/fs + 4/fs
101: 56/fs + 5/fs
110: 56/fs + 6/fs
111: 56/fs + 7/fs
100: 43/fs − 4/fs
101: 43/fs − 5/fs
110: 43/fs − 6/fs
111: 43/fs − 7/fs
100: 26/fs + 4/fs
101: 26/fs + 5/fs
110: 26/fs + 6/fs
111: 26/fs + 7/fs
100: 13/fs − 4/fs
101: 13/fs − 5/fs
110: 13/fs − 6/fs
111: 13/fs − 7/fs
26
18
10
0
0
0
2
0
-
-
CECWAV2
CECWAV0
25
17
0
0
9
0
1
0
-
-
TMPM361F10FG
CECWAVEN
24
16
0
0
8
0
0
0
-

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